Practical course in Digital Systems Design (PES)/ Digital Hardware Design Laboratory (DHL)

Notes:

Registration for the internship takes place online via the ILIAS portal of the KIT in the corresponding ILIAS course room (see ilias.studium.kit.edu). The registration will be activated on April 12, 2025.
The preliminary discussion will take place on Tuesday, April 22, 2025, at 2:00 pm in pool room 216 (Engesserstr. 5, building 30.10) of the Institute of Information Processing Technology (ITIV) and online via MS Teams (link in the ILIAS course). The actual practical course will be held on Tuesdays from 14:00 to 18:00. If the number of participants is high, a second session may be offered on Mondays from 14:00 to 18:00.
The number of internship places is limited. Online registration does not guarantee participation in the internship. The final decision on participation and the allocation of dates can only be made in the preliminary meeting. Students for whom the internship is a compulsory subject have priority.

Recommendations:

Knowledge of the design and design automation of electronic systems (e.g. HSO, No. 2311619 or HMS, No. 2311608).

Content:

Modern technologies such as artificial intelligence or image processing for autonomous driving require more and more computing power. There is a clear trend towards specially adapted computer chips and architectures. For this reason, the ability to create and design these is a very important tool for engineers today. In the practical course "Design of Digital Systems" (PES) you will have the opportunity to learn and apply these skills.
The design and simulation methods familiar from the lectures are practiced in practice. The commercial design and hardware synthesis tools from Xilinx, which are widely used in industry, and the simulation tool ModelSim from Mentor Graphics are used. Industrial hardware platforms are used to test the designs created.
The target platform of the practical course is the Digilent ZEDBOARD, which is equipped with a Zynq System-on-Chip (SoC) FPGA and contains both field-programmable logic parts and a dual-core ARM processor.
In the first part (four afternoons) of the practical course, basic knowledge of synthesis and simulation tools as well as the hardware description language VHDL is taught. You will first get to know the basic elements of an FPGA and gain an insight into the tool flow for programming FPGAs. You will also learn the basics of creating test benches. At the end of the basic phase, you will be able to implement common design patterns, such as finite state machines (FSMs), as well as complex circuit parts such as dividers or interfaces.
The project part of the internship will then begin, in which you will independently develop a hardware accelerator that the Zynq SoC system can use to process moving images. This involves extracting distinctive areas (regions) from the camera's raw data. These are then sent to the processor, which transmits the recognized regions to a monitor via an HDMI interface for visualization purposes.