VHDL-Online
VHDL Manual
VHDL Reference
Book download: Circuit Design with VHDL

VHDL-Online...a Hypertext-based VHDL Learning System

What is VHDL-Online?

The aim of VHDL-Online is to provide a learning system with a knowledge base that imparts VHDL knowledge to students and experienced engineers in self-study. By integrating the hypertext documents into the WorldWideWeb, a wide range of VHDL users will be addressed.

VHDL-Online consists of the modules VHDL-Manual and VHDL-Reference.

VHDL questions and answers

The questions and answers page of vhdl.org contains general questions about VHDL (e.g. contacts), a literature list, a product and service list (free and commercial) and a glossary.

VHDL-Online was developed by

• Institute for Information Processing Technology at the University of Karlsruhe
  • Dipl.-Ing. Bernhard Wunder,
  • Dipl.-Ing. Gunther Lehmann,
  • Dipl.-Ing. Peter Elter,
  • Dipl.-Ing. Michael Wolff.

German-language VHDL literature

• Circuit Design with VHDL - Synthesis, Simulation and Documentation of Digital Circuits
  G. Lehmann, B. Wunder, M. Selz, Franzis', Poing, 1994
• VLSI design - methods, procedure, automation
  Thomas Kropf, International Thomson Publishing, Bonn, 1995
• Abstract modeling of digital circuits from the functional model to the gate level
  Klaus tenHagen, Springer, Berlin-Heidelberg, 1995
• Detailed bibliography (also English literature)

Links to

• EDA Industry Working Groups
  Here is a comprehensive list of links on the subject!
• VHDL page (University of Hamburg)

This manual was created as an accompanying aid for a VHDL design practical course at the Institute of Information Processing Technology.

In addition to an introduction to hardware description languages and a typical VHDL design process, the manual explains the basic concepts of the hardware description language. Many pictures and examples complete this short introduction.

Contents

• 1. hardware description languages
  • 1.1 Tasks of a hardware description language
    • Design of complex systems / synthesis
    • Simulation of complex systems
    • Reuse / documentation
    • Data exchange
    • Advantages of standardizing the description language
  • 1.2 Viewpoints of the description and levels of abstraction
    • System level
    • Algorithmic level
    • Register transfer level
    • Logic level
    • Circuit level
• 2 The hardware description language VHDL
  • 2.1 Historical development of VHDL
  • 2.2 Design methodology with VHDL
  • 2.3 Structure of a VHDL model
    • Interface description (Entity)
    • Architecture
    • Configuration
    • Package
  • 2.4 Compiling and simulating
    • Design Libraries
    • Dependencies during compilation
    • Interrelationships during simulation
  • 2.3 Simulation algorithm
• 3 Building blocks of the VHDL language
  • 3.1 Character set
  • 3.2 Lexical elements
  • 3.3 Language constructs
    • 3.3.1 Primitives
      • operands
      • Operators
    • 3.3.2 Comments
    • 3.3.3 Statements
      • Declaration statements
      • Sequential statements
      • Concurrent statements
      • Configuration statements
    • 3.3.4 Syntactic frames
    • 3.3.5 Context instructions
• 4 Objects
  • 4.1 Object classes
  • 4.2 Type declarations
    • 4.2.1 Scalar data types
      • Enumerated types
      • Integer types
      • Floating point types
      • Physical types
      • Subtypes of scalar types
    • 4.2.2 Compound data types
      • Unconstrained fields (one-dimensional)
      • Restricted fields (one-dimensional)
      • Multidimensional fields
      • Sub-types of field types
      • Records
    • 4.2.3 Other types
      • Access types
      • Files
  • 4.3 Data declarations
• 5 The Entity
• 6 The Architecture
  • 6.1 Structural modeling
    • Component declaration
    • Component instantiation
    • Block statement
    • Generate statement
  • 6.2 Behavioral modeling
    • 6.2.1 Attributes
      • Type-related attributes:
      • Field-related attributes:
      • Block-related attributes:
      • Signal-related attributes:
    • 6.2.2 Concurrent instructions
      • Signal assignments
      • Assertions
      • Process instruction
    • 6.2.3 Sequential instructions
      • Assertions
      • Signal assignments
      • Variable assignment
      • WAIT statement
      • IF statement
      • CASE statement
      • NULL statement
      • LOOP statement
      • EXIT and NEXT statement
    • 6.2.4 Functions and procedures
• 7 Configuration
  • 7.1 Configuration of behavioral models
  • 7.2 Configuration of structural models
    • Block configuration instructions
    • Component configuration instructions
• 8 Timing in VHDL
  • 8.1 Simulation sequence
  • 8.2 Delay models
    • 8.2.1 Transport delay model
    • 8.2.2 Inertial delay model
• 9. context commands
• 10 Test environments
  • 10.1 Description of the stimuli
  • 10.2 Checking the expected responses
• 11. procedure for creating a VHDL model
  • 11.1 Preliminary remarks
  • 11.2 Creating the entity
  • 11.3 Creating architecture and configuration
    • 11.3.1 Structural modeling
    • 11.3.2 Behavioral modeling
  • 11.4 Description of stimuli, checking results and creating the testbench
• 12. the nine-valued logic system std_logic_1164
• 13. examples
  • 13.1 Multiplexer (structural model)
  • 13.2 Stimuli and response control for the 2:1 multiplexer
  • 13.3 Test environment for the 2:1 multiplexer
  • 13.4 Behavioral description of a D flip-flop
  • 13.5 Behavioral description of an automaton
• 14. literature

Circuit design with VHDL(Book download PDF)

Book loan(link to KIT library)

Publisher

Franzis' publishing house, Poing, 1994
hardcover, 315 pages, with diskette
ISBN 3-7723-6163-3

Authors

• Gunther Lehmann,
• Bernhard Wunder,
• Manfred Selz

Copyright

The authors Gunther Lehmann, Bernhard Wunder and Manfred Selz reserve the copyright.
Downloading the documents is only permitted for personal use. Reproduction for commercial purposes in any form (in whole or in part) is prohibited. Any non-commercial distribution (e.g. on the WWW or by e-mail) requires the express consent of the authors. The PDF documents may not be modified. This includes in particular the alteration or deletion of the copyright footer.

Overview

Since its company-independent standardization in 1987, the hardware description language VHDL and its support by commercial tools have become increasingly widespread. It has become the most important hardware description language in Europe. The broad vocabulary of VHDL enables the standardized description of electronic systems across different levels of abstraction. In conjunction with synthesis tools, significantly shorter development times and higher quality development results can be achieved.

The first VHDL book in German provides a comprehensive introduction to the syntax and semantics of the VHDL language. The language constructs are illustrated by numerous examples and exercises. The use of VHDL for simulation and synthesis in the design of digital circuits is also covered.

The inclusion of all VHDL language constructs allows the book to be used as a reference work for advanced VHDL users. However, the book is also aimed at VHDL beginners and is therefore particularly suitable for use in teaching and as supplementary reading for training courses.

In addition to the language standard IEEE Std 1076-1987, which is still frequently supported by VHDL tools today, the changes resulting from the change to the currently valid VHDL standard (IEEE Std 1076-1993) are also dealt with.

The book was written while we were working as research assistants at the Institute for Information Processing Technology (KIT) and the Chair of Computer-Aided Circuit Design (University of Erlangen-Nuremberg).

Gunther Lehmann, Bernhard Wunder, Manfred Selz.

Foreword

VHDL is a globally accepted standard for documentation, functional simulation and data exchange in the design of digital systems. Starting in the USA, VHDL has become a global success in recent years. The language is now used in many development departments; hardly any company can avoid using VHDL when designing digital hardware.
Over time, the field of application of VHDL has been extended in the direction of synthesis. This has opened up new, more productive paths in electronics development. The current efforts of international committees are moving towards an analog extension of the standard, which will help technological progress and the development towards mixed analog-digital systems and microsystems.
However, the problems that arise when using VHDL must not be concealed. It is a very powerful language that can only be properly mastered after a long period of practical use. Getting started is particularly difficult for hardware developers who have not yet worked intensively with a programming language. The psychological barrier should not be underestimated. In addition, the introduction of the "language" VHDL alone is not enough: the design methodology based on it requires a new way of working, a rethinking of familiar schemes and, last but not least, the use of new tools.

The initial technical problems (lack of manufacturer libraries, relatively slow simulation at gate level, no automated "backannotation") have already been largely eliminated. However, the fact that the VHDL language scope supported by different synthesis programs is limited and not identical poses a greater challenge.
Another serious problem is the strong dependence of the synthesis result on the quality of the VHDL description, aptly described by the catchphrase "what you write is what you get". In recent years, attempts have been made to relieve the developer of the burden of learning and fully understanding the language by introducing so-called "front-end tools". These tools generate VHDL code from a graphically defined behavioral description at the touch of a button, which is often referred to as "synthesis-compatible". This makes the design process more productive for many applications, because an automaton graph or a state chart is clearer and easier to overlook than pages of IF...THEN...ELSE and CASE statements.
The above-mentioned dependencies of the synthesis result on the VHDL code place high demands on these tools. However, since front-end and synthesis tools are usually offered by different manufacturers, the VHDL code generated is often not very optimized or even unsuitable for subsequent synthesis. The dependencies are so complex that the necessary manual changes to the source code can only be mastered by experts. It is therefore important to warn against blind faith in the results of this tool chain: Using VHDL only as a data exchange format without understanding the syntax and semantics can easily lead to unsatisfactory or even poor results. This is why books that provide the necessary background knowledge on the syntax and interpretation of the VHDL language are indispensable, even when using state-of-the-art development tools.

In this book, the authors have succeeded for the first time in providing a comprehensive German-language introduction to the syntax and semantics of the VHDL language and its application for simulation and synthesis, explaining it using simple examples. This is an important contribution to the dissemination of VHDL in German-speaking countries.

Karlsruhe, March 1994
Prof. Dr.-Ing. K. D. Müller-Glaser

Contents

Part A: Introduction

1 Design of electronic systems 16
    1.1 Motivation 16
    1.2 Design views 16
    1.3 Design levels 18
2 Motivation for a standardized HDL 23
    2.1 Complexity 23
    2.2 Data exchange 24
    2.3 Documentation 25
3 Historical development of VHDL 26
4 Structure of a VHDL description 29
    4.1 Interface description (Entity) 29
    4.2 Architecture 29
    4.3 Configuration 30
    4.4 Package 30
    4.5 Example of a VHDL model 31
5 Design views in VHDL 33
    5.1 Behavioral modeling 33
    5.2 Structural modeling 36
6 Design levels in VHDL 37
    6.1 Algorithmic level 37
    6.2 Register transfer level 38
    6.3 Logic level 39
7 Design methodology with VHDL 40
    7.1 Design flow 40
    7.2 VHDL software 43
8 Evaluation of VHDL 46
    8.1 Advantages of VHDL 46
    8.2 Disadvantages of VHDL 50

Part B: The VHDL language

1 General information 54
    1.1 VHDL'87 or VHDL'93 54
    1.2 Procedure and nomenclature 55
2 Language elements 56
    2.1 Language structure 56
    2.2 Character set 57
    2.3 Lexical elements 59
    2.4 Language constructs 67
3 Objects 71
    3.1 Object classes 71
    3.2 Data types and type declarations 72
    3.3 Object declarations 83
    3.4 Addressing objects 89
    3.5 Attributes 93
4 Structure of a VHDL model 94
    4.1 Libraries 94
    4.2 Interface description (Entity) 97
    4.3 Architecture 99
    4.4 Configuration 102
    4.5 Package 102
    4.6 Dependencies during compilation 104
5 Structural modeling 106
    5.1 Component declaration and inst.         108
    5.2 Block statement 113
    5.3 Generate statement 115
6 Behavioral modeling 119
    6.1 Operators 121
    6.2 Attributes 130
    6.3 Signal allocation and delay models 139
    6.4 Concurrent instructions 145
    6.5 Sequential instructions 152
    6.6 Subroutines 163
7 Configuring VHDL models 176
    7.1 Configuring behavioral models 177
    7.2 Configuration of structural models 177
8 Simulation sequence 186
    8.1 Delta cycle 186
    8.2 Time behavior of assignments 188
    8.3 Activation for the last delta cycle 190
9 Special features for signals 193
    9.1 Signal drivers and resolution functions 193
    9.2 Controlled signal assignments 197
    9.3 Controlled signals 198
10 Validity and visibility 201
    10.1 Validity 201
    10.2 Visibility 202
11 Special modeling techniques 204
    11.1 User-defined attributes 204
    11.2 Groups 207
    11.3 Overloading 209
    11.4 PORT MAP for structural models 214
    11.5 File I/O 215
    11.6 Pointers 221
    11.7 Ext. subroutines and architectures 227

Part C: Application of VHDL

1 Simulation 230
    1.1 Overview 230
    1.2 Simulation techniques 232
    1.3 Simulation phases 234
    1.4 Test environments 234
    1.5 Simulation of VHDL gate netlists 240
2 Synthesis 242
    2.1 Types of synthesis 242
    2.2 Use of synthesis programs 248
    2.3 Synthesis of combined circuits 251
    2.4 Synthesis of sequential circuits 263
    2.5 Optimization of constraints 269
    2.6 Resource requirements for synthesis 274

Part D: Appendix

1 Packages 278
    1.1 The package standard 278
    1.2 The package textio 279
    1.3 IEEE package 1164 281
2 VHDL exercise examples 288
    2.1 Basic VHDL constructs 288
    2.2 Complex models 291
3 VHDL committees and sources of information 298
    3.1 VHDL News Group 298
    3.2 VHDL International 299
    3.3 VHDL Forum for CAD in Europe 299
    3.4 European CAD Standardization Initiative 300
    3.5 AHDL 1076.1 Working Group 301
    3.6 VHDL Initiative Towards ASIC Libraries 302
    3.7 E-mail Synopsys Users Group 302
4 Disk contents 303

Literature 304
Subject index 309