Developing a mapping tool for adaptive AI accelerators

Context

The computational complexity of modern AI algorithms is still a challenge for many computer systems today. Hardware acceleration for these algorithms is therefore essential. However, a given neural network, e.g. in the standard ONNX format, cannot be executed directly on a hardware accelerator - mapping and scheduling must be performed to map the algorithm to the available hardware. Such tools are available for simple accelerators and e.g. for GPUs, but often do not find a very good mapping or are not applicable to different accelerator designs.

Tasks

In this thesis, a mapping tool for an adaptive hardware accelerator will be developed. Building on existing tools like Apache TVM, the resulting tool should be able to find good mappings for different configurations of an accelerator. The accelerator is available as an FPGA design in HDL form and can be configured and sized differently. Operations that may not be supported by the accelerator can be performed in software on a RISC-V processor. As part of the literature review, various mapping tools from industry and academia need to be investigated for their suitability, and a selection of neural networks needs to be compiled against which the approach can be tested.

Requirements

• Interest in hardware related software development and working with FPGA prototyping boards as well as compiler development like TVM
• Knowledge of Python & C++ for familiarization with existing software projects
• Basic knowledge in HDL (VHDL/Verilog) advantageous