M. Sc. Fabian Kreß

  • 19.12.2024
  • Ressource-aware Deep Neural Network Inference Partitioning in Embedded Systems
  • Group: Prof. Becker

  • Corrector: Prof. Dr.-Ing. Mladen Berekovic (Uni zu Lübeck)

Research interests

Design Space Exploration for Embedded AI Applications

Today, applications such as object detection or classification in the field of autonomous driving are usually realized by using Artificial Intelligence (AI). In contrast to conventional algorithms, AI can often provide more precise and reliable results. However, AI-based applications usually require to process a huge amount of operations. In the context of embedded platforms, it is therefore important to investigate, how latency, data throughput and power consumption of the system can be optimized considering the constraints imposed by the application.

Emerging Non-Volatile Memory Technologies

In recent decades, novel Non-Volatile Memory technologies (NVMs), such as MRAM or ReRAM, have been introduced and developed further. Emerging NVMs in general consume less static power than SRAM or DRAM and require only a fraction of the area compared to an SRAM cell. Additionally, these technologies enable efficient In-Memory Computing to accelerate matrix-vector multiplications, for example. Therefore, NVMs offer the opportunity to rethink established memory hierarchies and computer architectures for future systems.

Embedded FPGA Architecture and Toolchain

Embedded FPGAs (eFPGA) add flexibility to the entire system by allowing hardware reconfiguration during runtime. Hence, various workloads can be accelerated and the hardware accelerators themselves can also be updated. However, the initial layout of the eFPGA has to be defined before tape-out. This involves not only determining the number of LUTs but also the design of application-specific IPs. The integration of an eFPGA thus increases the complexity in the design phase which requires improved toolchains.

Teaching

Supervised student works (selection)

  • SA: “Emerging Memory Technologies and their use in new System Architectures”
  • BA: „Hypervisor-based Framework for Evaluation of emerging Memory Technologies“
  • SA: „Emerging Memory Technologies in future Computer Architectures“
  • MA: „A Low-Power RISC-V Core for Tiny Machine Learning“
  • MA: „Development of an FPGA Synthesis-Toolchain for automated Integration of Hybrid Flip-Flops“
  • SA: „Evaluation of external Memories for Neural Network Inference in IoT devices“
  • SA: „Energy-efficient AI accelerators for Online Handwriting Recognition“
  • SA: „Evaluation of Optimization Strategies for Neural Networks in the Digipen for Online Handwriting Recognition“
  • MA: „Hardware/Software Co-Design of an Ultra-Low Power RISC-V Platform for Online Handwriting Recognition“

Publications


2024
Conference Papers
LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator
Kreß, F.; Serdyuk, A.; Kobsar, D.; Hotfilter, T.; Höfer, J.; Harbaum, T.; Becker, J.
2024. 2024 IEEE 37th International System-on-Chip Conference (SOCC), Dresden, Germany, 16-19 September 2024, 126–131, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737863
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems
Kreß, F.; El Annabi, E. M.; Hotfilter, T.; Hoefer, J.; Harbaum, T.; Becker, J.
2024. 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1st-3rd July 2024, Knoxville, 39–44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI61997.2024.00019
VHDL Crash Course: A Multimedia-Based Teaching Approach
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Harbaum, T.; Becker, J.
2024. 2024 IEEE 3rd German Education Conference (GECon), Munich, Germany, 05-07 August 2024, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/GECon62014.2024.10734007
KIHT: Kaligo-Based Intelligent Handwriting Teacher
Harbaum, T.; Serdyuk, A.; Kreß, F.; Hamann, T.; Barth, J.; Kämpf, P.; Imbert, F.; Soullard, Y.; Tavenard, R.; Anquetil, E.; Delahaie, J.
2024. Proceedings - 2024 Design, Automation and Test in Europe Conference and Exhibition (DATE), 6 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE58400.2024.10546623
A Challenge-Based Blended Learning Approach for an Introductory Digital Circuits and Systems Course
Hoefer, J.; Gauß, M.; Adams, M.; Kreß, F.; Kempf, F.; Karle, C.; Harbaum, T.; Barth, A.; Becker, J.
2024. 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 19-22 May 2024, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISCAS58744.2024.10557955
HW/SW Co-Design for Integrated AI Systems: Challenges, Use Cases and Steps Ahead
Harbaum, T.; Topko, I.; Serdyuk, A.; Fürst-Walter, I.; Kreß, F.; Becker, J.
2024. 3rd Workshop on Deep Learning for IoT (DL4IoT-2024)
Context-Aware Layer Scheduling for Seamless Neural Network Inference in Cloud-Edge Systems
Stammler, M.; Sidorenko, V.; Kreß, F.; Schmidt, P.; Becker, J.
2024. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapur, 18th-21st December 2023, 97–104, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00022
Audio & Video
[VHDL Crash Course] Testbenches - How to Test your VHDL model
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Concurrent Modeling - The Register-Transfer-Level Mindset
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Sequential Modeling - Introduction to If and Case Statements
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Processes in VHDL - How to model sequential Algorithms
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Avoiding Code Duplicates - VHDL Module Parameters and Architectures
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Bit Vectors and Numbers - Basic VHDL Types
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Entity and Architecture - Introduction to the basic VHDL structure
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] HDLs in general - What are HDLs used for
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] How to Learn with Videos - Introduction to Self-regulated Learning
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
2023
Journal Articles
CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems
Kreß, F.; Sidorenko, V.; Schmidt, P.; Hoefer, J.; Hotfilter, T.; Walter, I.; Harbaum, T.; Becker, J.
2023. Computer Networks, 229, Article no: 109759. doi:10.1016/j.comnet.2023.109759
Conference Papers
ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT Applications
Kreß, F.; Serdyuk, A.; Hiegle, M.; Waldmann, D.; Hotfilter, T.; Hoefer, J.; Hamann, T.; Barth, J.; Kämpf, P.; Harbaum, T.; Becker, J.
2023. 26th Euromicro Conference on Digital System Design (DSD 2023), 569–576, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD60849.2023.00084
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency
Hotfilter, T.; Hoefer, J.; Merz, P.; Kreß, F.; Kempf, F.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 36th International System-on-Chip Conference (SOCC), Santa Clara, USA, 05-08 September 2023, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC58585.2023.10256738
Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing
Kreß, F.; Pfau, J.; Kempf, F.; Schmidt, P.; He, Z.; Harbaum, T.; Becker, J.
2023. 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), 31st October - 1st November 2023, Aalborg, Denmark, 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS58970.2023.10305469
A Hardware-Aware Sampling Parameter Search for Efficient Probabilistic Object Detection
Hoefer, J.; Hotfilter, T.; Kreß, F.; Qiu, C.; Harbaum, T.; Becker, J.
2023. Computer Vision Systems – 14th International Conference, ICVS 2023, Vienna, Austria, September 27–29, 2023. Ed.: H. Christensen, 299–309, Springer Nature Switzerland. doi:10.1007/978-3-031-44137-0_25
A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs
Hotfilter, T.; Höfer, J.; Kreß, F.; Kempf, F.; Kraft, L.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 1–5, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/AICAS57966.2023.10168566
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators
Hoefer, J.; Kempf, F.; Hotfilter, T.; Kreß, F.; Harbaum, T.; Becker, J.
2023. Proceedings of the Great Lakes Symposium on VLSI 2023, 287–292, Association for Computing Machinery (ACM). doi:10.1145/3583781.3590226
An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload
Hotfilter, T.; Schmidt, P.; Höfer, J.; Kreß, F.; Harbaum, T.; Becker, J.
2023. DroneSE and RAPIDO: System Engineering for constrained embedded systems, 73–78, Association for Computing Machinery (ACM). doi:10.1145/3579170.3579258
Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA
Kreß, F.; Hoefer, J.; Hotfilter, T.; Walter, I.; El Annabi, E. M.; Harbaum, T.; Becker, J.
2023. Machine Learning and Principles and Practice of Knowledge Discovery in Databases. Hrsg.: I. Koprinska. Pt. 1, 557–568, Springer International Publishing. doi:10.1007/978-3-031-23618-1_37
2022
Conference Papers
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors
Kempf, F.; Höfer, J.; Kreß, F.; Hotfilter, T.; Harbaum, T.; Becker, J.
2022. Conference Proceedings: 2022 IEEE 35th International System-on-Chip Conference (SOCC) Ed.: S. Sezer, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC56010.2022.9908110
Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA
Hotfilter, T.; Kreß, F.; Kempf, F.; Becker, J.; Baili, I.
2022. 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Nicosia, Cyprus, 04-06 July 2022, 371–372. doi:10.1109/ISVLSI54635.2022.00082
Hardware-aware Partitioning of Convolutional Neural Network Inference for Embedded AI Applications
Kreß, F.; Hoefer, J.; Hotfilter, T.; Walter, I.; Sidorenko, V.; Harbaum, T.; Becker, J.
2022. 18th International Conference on Distributed Computing in Sensor Systems (DCOSS), 133–140, IEEEXplore. doi:10.1109/DCOSS54816.2022.00034
Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen
Kreß, F.; Serdyuk, A.; Hotfilter, T.; Höfer, J.; Harbaum, T.; Becker, J.; Hamann, T.
2022. 2022 11th Mediterranean Conference on Embedded Computing (MECO). Ed.: IEEE, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MECO55406.2022.9797131
Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs
Hotfilter, T.; Kreß, F.; Kempf, F.; Becker, J.; Haro, J. M. De; Jiménez-González, D.; Moretó, M.; Álvarez, C.; Labarta, J.; Baili, I.
2022. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 14-23 March 2022, 628–631, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE54114.2022.9774716
2021
Conference Papers
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips
Hotfilter, T.; Hoefer, J.; Kreß, F.; Kempf, F.; Becker, J.
2021. IEEE 34th International System-on-Chip Conference (SOCC), 14th-17th September 2021, Las Vegas, Nevada, USA, 83–88, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC52499.2021.9739212
Transparent Near-Memory Computing with a Reconfigurable Processor
Lesniak, F.; Kreß, F.; Becker, J.
2021. Applied Reconfigurable Computing. Ed.: S. Derrien, 221–231, Springer Nature Switzerland. doi:10.1007/978-3-030-79025-7_15
2018
Conference Papers
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, VN, September 12-14, 2018, 138–145, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC2018.2018.00033
Presentations
In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), Hanoi, Vietnam, September 12–14, 2018