Summa cum laude for Johannes Pfau

Hard work and determination have led to this academic success with the distinction of "Summa cum laude".

The aim of Johannes' dissertation entitled "RFET Reconfigurable Devices: Power Aware FPGA Architectures and Toolflow" was to introduce and investigate active power management techniques in FPGA architectures as part of the PARFAIT project. The solution approach presented uses fine-grained, partially dynamic reconfiguration to temporarily replace application logic with management logic at runtime.

This realizes a measurement of the current runtime delay in the corresponding logic elements, whereby the application is not affected. Based on the measurement results, the runtime delay is dynamically adjusted in order to reduce the static power dissipation.

The system was simulated using RFET and SOI technology, achieving up to a 36-fold reduction in static power dissipation.

We wish Johannes continued success for all the great things he will achieve in the future and look forward to seeing him again at the next ITIV alumni meeting.

Congratulations!