Hardware Implementation of Anomaly Detection Strategies in Hardware Accelerators

Context

There exist a plethora of strategies to detect anomalies in machine learning models that are based on the classification of layer traces into different classes of execution patterns. While these methods are researched using powerful graphics cards, a hardware implementation on dedicated embedded accelerators is not present. The work of this task is to implement a dedicated hardware component that is parameterizable and configurable to detect anomalies in parallel to layer inference.

Tasks

Implementing a hardware component to classify layer traces of machine learning models into normal behavior or anomaly.

Requirements

• Good knowledge in hardware development using HLS languages
• Good knowledge in machine learning methods and models