Research interests

Design Space Exploration for Embedded AI Applications

Today, applications such as object detection or classification in the field of autonomous driving are usually realized by using Artificial Intelligence (AI). In contrast to conventional algorithms, AI can often provide more precise and reliable results. However, AI-based applications usually require to process a huge amount of operations. In the context of embedded platforms, it is therefore important to investigate, how latency, data throughput and power consumption of the system can be optimized considering the constraints imposed by the application.

Emerging Non-Volatile Memory Technologies

In recent decades, novel Non-Volatile Memory technologies (NVMs), such as MRAM or ReRAM, have been introduced and developed further. Emerging NVMs in general consume less static power than SRAM or DRAM and require only a fraction of the area compared to an SRAM cell. Additionally, these technologies enable efficient In-Memory Computing to accelerate matrix-vector multiplications, for example. Therefore, NVMs offer the opportunity to rethink established memory hierarchies and computer architectures for future systems.

Embedded FPGA Architecture and Toolchain

Embedded FPGAs (eFPGA) add flexibility to the entire system by allowing hardware reconfiguration during runtime. Hence, various workloads can be accelerated and the hardware accelerators themselves can also be updated. However, the initial layout of the eFPGA has to be defined before tape-out. This involves not only determining the number of LUTs but also the design of application-specific IPs. The integration of an eFPGA thus increases the complexity in the design phase which requires improved toolchains.

Teaching

Supervised student works (selection)

SA: “Emerging Memory Technologies and their use in new System Architectures”
BA: „Hypervisor-based Framework for Evaluation of emerging Memory Technologies“
SA: „Emerging Memory Technologies in future Computer Architectures“
MA: „A Low-Power RISC-V Core for Tiny Machine Learning“
MA: „Development of an FPGA Synthesis-Toolchain for automated Integration of Hybrid Flip-Flops“
SA: „Evaluation of external Memories for Neural Network Inference in IoT devices“
SA: „Energy-efficient AI accelerators for Online Handwriting Recognition“
SA: „Evaluation of Optimization Strategies for Neural Networks in the Digipen for Online Handwriting Recognition“
MA: „Hardware/Software Co-Design of an Ultra-Low Power RISC-V Platform for Online Handwriting Recognition“

Student works to be assigned
title	type