Becker

Prof. Dr.-Ing. Dr. h. c. Jürgen Becker

  • Engesserstr. 5

    76131 Karlsruhe

Prof. Dr.-Ing. Dr. h. c. Jürgen Becker

Lebenslauf

Studium der Informatik an der Universität Kaiserslautern (Vertiefung Technische Informatik), Abschluss 1992 mit dem Diplom. Von 1992 bis 1997 Wissenschaftlicher Mitarbeiter am Lehrstuhl für Rechnerstrukturen mit Forschungsinteressen in Rechnerarchitekturen (rekonfigurierbare Akzeleratoren), Hardware/Software Codesign und parallelisierenden Compilern, Administrator des europäischen Entwurfsprojekts EUROCHIP an der Universität Kaiserslautern. Abschluss in 1997 mit der Promotion (Dr.-Ing.). Von 1997 bis 2001 Wissenschaftlicher Assistent im Fachbereich Elektrotechnik und Informationstechnik (Lehrstuhl Mikroelektronische Systeme) an der TU Darmstadt. In der Lehre wurden High-Level Synthese und VLSI CAD Algorithmen vertreten, in der industrienahen Forschung Schwerpunkte in dynamisch rekonfigurierbaren Systems-on-Chip und IP-basierten Anwendungsabbildungsverfahren bearbeitet.

2001 Ruf an die Universität Karlsruhe (TH), Institutsleitung des Instituts für Technik der Informationsverarbeitung (ITIV) in der Fakultät für Elektrotechnik und Informationstechnik, Direktor der Gruppe Embedded Systems and Sensors Engineering (ESS) des Forschungszentrum Informatik (FZI) und von 2001 bis 2005 Stellvertretender Direktor (geschäftsführend) des International Department an der Universität Karlsruhe (TH). Landeslehrpreisträger Baden-Württemberg 2003.

Autor und Coautor von mehr als 400 Veröffentlichungen (und mehr als 30 Patenten) mit Schwerpunkt Architekturen und Entwurf von Eingebetteten Elektronischen Systemen mit vielfältigen u.a. industriellen Projekten, insbesondere im Bereich Automotive. Aktiv als Tagungsleiter und in zahlreichen Programmausschüssen internationaler Konferenzen und Workshops. Professor Becker war von Oktober 2005 als Prorektor der Universität Karlsruhe (TH), bzw. von Oktober 2009 bis März 2012 als Chief Higher Education Officer (CHEO) des KIT zuständig für den Bereich Studium und Lehre. Prof. Becker war von 2012 bis 2014 CLUSTER Generalsekretär (Consortium aus 12 Universitäten).

2013 hat Prof. Becker die Ehrendoktorwürde (Dr. h. c.) der Technischen und Wirtschaftswissenschaftlichen Universität (TWU) Budapest erhalten.

GruppenbildITIV
Prof. Becker mit seinen internen und externen Doktoranden

Forschung

ForschungsbereicheITIV

Leitung des Forschungsbereichs „Embedded Electronic Systems“ mit den Forschungsschwerpunkten

  • System-on-Chip (SoC), Network-on-Chip (NoC)
  • Hardware Software Codesign
  • Multi-Core-Prozessor-Architekturen
  • HPC- & KI-basierte Systemintegration
    • Spezifische Beschleuniger
    • Zuverlässigkeit, Echtzeit und Leistung
  • Dynamisch rekonfigurierbare Systeme
  • Hardware-Synthesemethoden und Mehrdomänen-Modellierungs- und Simulationstechniken
  • Cyber-Physical Systems (CPS)

Leitung des Bereichs Embedded Systems and Sensors Engineering (ESS) am FZI

Auszeichungen 

Leitende Funktionen und Rollen

Konferenzen

  • FPL (International Conference on Field-Programmable Logic and Applications)
  • RAW (Reconfigurable Architecture Workshop)
  • ARC (International Symposium on Applied Reconfigurable Computing)
  • ISVLSI (IEEE Computer Society Annual Symposium on VLSI)
  • IEEE SOCC (IEEE International System-on-Chip Conference)
  • PATMOS (International Workshop on Power And Timing Modeling, Optimization and Simulation)

Projekte (Auswahl)

Projekt XANDAR

Software und Hardware für vernetzte eingebettete Systeme müssen höchste Anforderungen an Sicherheit, Echtzeitfähigkeit, Energie- und Ressourceneffizienz erfüllen. Im Projekt XANDAR erarbeiten acht Partner aus Wissenschaft und Wirtschaft eine komplette Werkzeugkette (Toolchain) zur Softwareentwicklung und Hardware-Software-Integration für komplexe Anwendungen auf zukünftigen Prozessorplattformen, beispielsweise in autonomen Fahrzeugen und für zukünftige Urban-Air-Mobility-Konzepte.

(https://www.itiv.kit.edu/7429.php)
 

Projekt ARAMiS II

Zukünftige sicherheitskritische Anwendungen in der Automobil- und Luftfahrt-Industrie, aber auch das Zukunftsthema Industrie 4.0 zeigen einen deutlich steigenden Bedarf an digitaler Rechenleistung.
Diesem Bedarf entspricht, dass auch die Prozessoren von eingebetteten Systemen in nächster Zeit auf Multicore-Technologie basieren werden, die in anderen Anwendungsgebieten wie PCs, Tablets und Smartphones längst erfolgreich verwendet werden.
(https://www.itiv.kit.edu/5158.php)
 

Projekt ARAMiS

ARAMiS (Automotive, Railway and Avionics Multicore Systems) hat zum Ziel, durch den Einsatz von Multicore-Technologie in den Mobilitätsdomänen Automobil, Avionik und Bahn die technologische Basis zur weiteren Erhöhung von Sicherheit, Verkehrseffizienz und Komfort zu schaffen.
 

Open6G Hub

6G stellt eine drahtlose Kommunikation in unserer zukünftig hochvernetzten Welt dar. Es ermöglicht die Vernetzung autonomer Geräte, Fahrzeuge und Drohen und schafft die Grundlage für zukünftig benötigte hohe Kommunikationsbandbreiten. Innerhalb des Projekts Open 6G Hub wird die Entwicklung eines globalen 6G-Standards vorangetrieben, um zum einen gesellschaftliche Prioritäten zu berücksichtigen, als auch die Position Deutschlands und Europas im internationalen Wettbewerb um 6G zu stärken.
(https://www.itiv.kit.edu/201_8061.php)

CeCaS – Central Car Server

Automatisierte, vernetzte und elektrifizierte Fahrzeuge nehmen Fahrt auf. Doch fehlen zur vollen Alltagstauglichkeit energieeffiziente und kostengünstige High-End Compute Plattformen, die bei vollständiger Automotive Qualifizierung (ASIL-D) mit den Anforderungen an Rechenleistung und Komplexität Schritt halten. Insbesondere KI-basierte Themenbereiche wie das Autonome Fahren erfordern maßgeschneiderte, echtzeittaugliche und energieeffiziente Hochleistungsprozessoren. Es geht um Performance und Sicherheit aus einem Guss – und die Zukunftsfähigkeit der Automobilindustrie.
(https://www.itiv.kit.edu/201_8769.php)

EMDRIVE

Das übergeordnete Ziel von EMDRIVE ist ein hierarchisches, skalierbares Plattformkonzept für verteilte heterogene Automotive-Echtzeit Rechennetzwerk-Architekturen – Centralized High-Performance Automotive RT-Compute Boardnets (Sensor2Edge). Die Ergebnisse sollen über das Projekt hinaus in die Automobilproduktion einfließen.
(https://www.itiv.kit.edu/201_8233.php)

BELLE II

Das Belle II-Experiment in Tsukuba, Japan bietet einzigartige Möglichkeiten zur Erforschung seltener τ-Zerfälle und zum Studium bestimmter Formen von Dunklen Photonen und Physik jenseits des Standard Modells. Dazu werden Elektronen und ihre Protonen im asymmetrischen SuperKEKB auf fast Lichtgeschwindigkeit beschleunigt, um diese im Belle II Detektor zu kollidieren. Die dabei entstehenden Zerfallsprodukte werden gemessen und aufgezeichnet, um die Daten später zu analysieren. Dabei ist es wichtig, interessante neue Daten von bereits bekannten Zerfällen zu unterscheiden. Um dies zu gewährleisten, ist ein zweistufiges Trigger System installiert, das alle Zerfälle analysiert. Die erste Stufe besteht aus einem gepipelineten todzeitlosen FPGA System. Die zweit Stufe dagegen wird Software basiert auf Großrechnern berechnet.
(https://www.itiv.kit.edu/201_8048.php)

Innovation

 

emmtrix Technologies GmbH
Die emmtrix Technologies GmbH ist ein Spin-Off des Instituts für Informationsverarbeitung (ITIV) am Karlsruher Institut für Technologie (KIT). Das Unternehmen entwickelt Softwarewerkzeuge, welche die Programmierung von Mehrkernprozessoren in eingebetteten Systemen (z.B. Fahrassistenzsysteme) signifikant vereinfacht und optimiert.
(www.emmtrix.com)

Publikationen


2024
Zeitschriftenaufsätze
Machine-Learning-based Side-Channel Attack Detection for FPGA SoCs
Bauer, L.; Nassar, H.; Khan, N.; Becker, J.; Henkel, J.
2024. IEEE Transactions on Circuits and Systems for Artificial Intelligence, 1–12. doi:10.1109/TCASAI.2024.3483118
Characterization of the radiation tolerant ToASt ASIC for the readout of the PANDA MVD strip detector
Lenta, F.; Calvo, D.; Cossio, F.; Mazza, G.; Wheadon, R.; Becker, J.; Brinkmann, K.-T.; Caselle, M.; Kopmann, A.; Manzhura, O.; Mattiazzo, S.; Peter, M.; Sidorenko, V.; Staněk, P.; Stockmanns, T.; Tomášek, L.; Tröll, N.; Unger, K. L.; Zaunick, H.-G.
2024. Journal of Instrumentation, 19 (04), Art.-Nr.: C04047. doi:10.1088/1748-0221/19/04/C04047
The data acquisition system for the PANDA Micro-Vertex Detector
Manzhura, O.; Caselle, M.; Ardila-Perez, L. E.; Calvo, D.; Chilingaryan, S.; Cossio, F.; Dritschler, T.; Kopmann, A.; Lenta, F.; Mazza, G.; Peter, M.; Sidorenko, V.; Staněk, P.; Stockmanns, T.; Tomášek, L.; Tröll, N.; Unger, K. L.; Zaunick, H.-G.; Becker, J.; Brinkmann, K.-T.
2024. Journal of Instrumentation, 19 (03), Art.-Nr.: C03036. doi:10.1088/1748-0221/19/03/C03036
Time error accumulation in a hierarchical time and clock distribution network with deterministic optical links
CBM Collaboration; Sidorenko, V.; Müller, W. F. J.; Emschermann, D.; Zabolotny, W.; Fröhlich, I.; Becker, J.
2024. Journal of Instrumentation, 19 (03), Art.-Nr.: C03014. doi:10.1088/1748-0221/19/03/C03014
Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle Physics
Neu, M.; Becker, J.; Dorwarth, P.; Ferber, T.; Reuter, L.; Stefkova, S.; Unger, K.
2024. Computing and Software for Big Science, 8 (1), Artl.Nr.: 8. doi:10.1007/s41781-024-00117-0
Mechatronic Coupling System for Cooperative Manufacturing with Industrial Robots
Mühlbeier, E.; Bauer, V.; Schade, F.; Gönnheimer, P.; Becker, J.; Fleischer, J.
2024. 56th CIRP International Conference on Manufacturing Systems 2023 Hrsg.: Mpofu, Khumbulani; Sacks, Natasha; Damm, Oliver, 120, 744–749. doi:10.1016/j.procir.2023.09.069
Proceedingsbeiträge
A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event Interpretation
Neu, M.; Karle, C.; Schmidt, P.; Höfer, J.; Harbaum, T.; Becker, J.
2024. IEEE 37th International System-on-Chip Conference (SOCC 2024), 6 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737798
Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G
Karle, C.; Neu, M.; Nuss, B.; Witte, L.; Scheder, A.; Waldner, E.; Shkurtaj, E.; Harbaum, T.; Becker, J.
2024. IEEE 37th International System-on-Chip Conference (SOCC 2024), 6 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737777
Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development
Karle, C.; Neu, M.; Nuss, B.; Chen, J.; Witte, L.; Scheder, A.; Harbaum, T.; Becker, J.
2024. IEEE 37th International System-on-Chip Conference (SOCC 2024), 6 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737765
LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator
Kreß, F.; Serdyuk, A.; Kobsar, D.; Hotfilter, T.; Höfer, J.; Harbaum, T.; Becker, J.
2024. 2024 IEEE 37th International System-on-Chip Conference (SOCC), Dresden, Germany, 16-19 September 2024, 126–131, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC62300.2024.10737863
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems
Kreß, F.; El Annabi, E. M.; Hotfilter, T.; Hoefer, J.; Harbaum, T.; Becker, J.
2024. 2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1st-3rd July 2024, Knoxville, 39–44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI61997.2024.00019
Enhancing Force Sensing Capabilities in Exoskeleton Interfaces Using Compliant Actuator-Sensor Units - A User Study
Alagi, H.; Fischer, N.; Behrends, K.; Ftirst-Walter, I.; Becker, J.; Beigl, M.; Mathis-Ullrich, F.; Hein, B.
2024. 2024 10th IEEE RAS/EMBS International Conference for Biomedical Robotics and Biomechatronics (BioRob), Heidelberg, Germany, 01-04 September 2024, 889–894, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/BioRob60516.2024.10719794
VHDL Crash Course: A Multimedia-Based Teaching Approach
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Harbaum, T.; Becker, J.
2024. 2024 IEEE 3rd German Education Conference (GECon), Munich, Germany, 05-07 August 2024, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/GECon62014.2024.10734007
Ph.D. Project: Compiler-Driven Hardware/Software Co- Design for Embedded AI
Schmidt, P.; Becker, J.
2024. 2024 IEEE 32nd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Orlando, 5th-8th May 2024, 241 – 242, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FCCM60383.2024.00055
XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems
Dörr, T.; Schade, F.; Becker, J.; Keramidas, G.; Petrellis, N.; Kelefouras, V.; Mavropoulos, M.; Antonopoulos, K.; Antonopoulos, C. P.; Voros, N.; Ahlbrecht, A.; Zaeske, W.; Janson, V.; Nöldeke, P.; Durak, U.; Panagiotou, C.; Karadimas, D.; Adler, N.; Reichmann, C.; Sailer, A.; u. a.
2024. Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 25-27 March 2024, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE58400.2024.10546852
A Full-System Approach to Multi-Valued Logic Design: (PhD Forum Paper)
Gutermann, A.; Becker, J.
2024. 2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP), Hong Kong, 24th-26th July 2024, 226 – 227, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ASAP61560.2024.00052
Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary Dataflow
Lesniak, F.; Gutermann, A.; Harbaum, T.; Becker, J.
2024. GLSVLSI ’24: Proceedings of the Great Lakes Symposium on VLSI 2024, 151 – 157, Association for Computing Machinery (ACM). doi:10.1145/3649476.3658737
A Challenge-Based Blended Learning Approach for an Introductory Digital Circuits and Systems Course
Hoefer, J.; Gauß, M.; Adams, M.; Kreß, F.; Kempf, F.; Karle, C.; Harbaum, T.; Barth, A.; Becker, J.
2024. 2024 IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, 19-22 May 2024, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISCAS58744.2024.10557955
Towards the on-device Handwriting Trajectory Reconstruction of the Sensor Enhanced Pen
Serdyuk, A.; Kreβ F.; Hiegle, M.; Harbaum, T.; Becker, J.; Imbert, F.; Soullard, Y.; Tavenard, R.; Anquetil, E.; Barth, J.; Kämpf, P.
2024. 2023 IEEE 9th World Forum on Internet of Things (WF-IoT), Aveiro, 12th - 27th October 2023, 01–06, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/WF-IoT58464.2023.10539488
HW/SW Co-Design for Integrated AI Systems: Challenges, Use Cases and Steps Ahead
Harbaum, T.; Topko, I.; Serdyuk, A.; Fürst-Walter, I.; Kreß, F.; Becker, J.
2024. 3rd Workshop on Deep Learning for IoT (DL4IoT-2024)
Automatic Deployment of Embedded Real-Time Software Systems to Hypervisor-Managed Platforms
Schade, F.; Dörr, T.; Ahlbrecht, A.; Janson, V.; Durak, U.; Becker, J.
2024. 2023 26th Euromicro Conference on Digital System Design (DSD), Golem, 6th - 8th September 2023, 436 – 443, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD60849.2023.00067
Mitigating Masking in Automotive Communication Systems: Modeling and Hardware Generation
Stammler, M.; Hamann, M.; Harbaum, T.; Becker, J.
2024. 2023 26th Euromicro Conference on Digital System Design (DSD), Golem, 6th - 8th September 2023, 561 – 568, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD60849.2023.00083
Low-latency inter-domain communication on the Xen hypervisor
Lesniak, F.; Harbaum, T.; Becker, J.
2024. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapur, 18th - 21st December 2023, 340–346, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00057
Context-Aware Layer Scheduling for Seamless Neural Network Inference in Cloud-Edge Systems
Stammler, M.; Sidorenko, V.; Kreß, F.; Schmidt, P.; Becker, J.
2024. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapur, 18th-21st December 2023, 97–104, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00022
Forschungsdaten
SciTS v2.0-rc1
Mostafa, J.; Melissano, S.; Chilingaryan, S.; Kopmann, A.; Becker, J.
2024. doi:10.5281/zenodo.10580527
Audio & Video
[VHDL Crash Course] Testbenches - How to Test your VHDL model
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Concurrent Modeling - The Register-Transfer-Level Mindset
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Sequential Modeling - Introduction to If and Case Statements
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Processes in VHDL - How to model sequential Algorithms
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Avoiding Code Duplicates - VHDL Module Parameters and Architectures
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Bit Vectors and Numbers - Basic VHDL Types
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] Entity and Architecture - Introduction to the basic VHDL structure
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] HDLs in general - What are HDLs used for
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
[VHDL Crash Course] How to Learn with Videos - Introduction to Self-regulated Learning
Kreß, F.; Sidorenko, V.; Topko, I.; Unger, K.; Schneider, M.; Becker, J.
2024
Dissertationen
Multigranulare Optimierung für heterogene Multicore-Systeme. Dissertation
Wolf, O.
2024, November 14. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000176033
Pattern-Based Logical Isolation for Safety-Critical Multicore Systems. Dissertation
Dörr, T.
2024, Oktober 28. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000175388
RFET Reconfigurable Devices: Power Aware FPGA Architectures and Toolflow. Dissertation
Pfau, J.
2024, November 15. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000174452
Development of methods for control of a massively parallel 3D USCT system. Dissertation
Lu, Z.
2024, August 21. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000173484
Efficient Optimization of Convolutional Neural Networks for Modern Embedded High-Performance Applications. Dissertation
Hotfilter, T.
2024, August 14. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000173259
Hypervisor-basierte Partitionierung von Mixed-Criticality-Anwendungen in heterogenen eingebetteten Systemen. Dissertation
Schade, F.
2024, Juli 23. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000172536
2023
Buchaufsätze
A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment
Unger, K.; Becker, J.; Kiesling, C.; Ma, Y.; Meggendorfer, F.; Neu, M.; Schmidt, E.; Zweigart, U.
2023. Applied Reconfigurable Computing. Architectures, Tools, and Applications – 19th International Symposium, ARC 2023, Cottbus, Germany, September 27–29, 2023, Proceedings. Ed.: F. Palumbo, 173–184, Springer Nature Switzerland. doi:10.1007/978-3-031-42921-7_12
Zeitschriftenaufsätze
Modular Hardware/Software Architecture for Edge Units in Highly Flexible Manufacturing Systems
Schade, F.; Kreutzer, M.; Mühlbeier, E.; Gerlitz, E.; Gönnheimer, P.; Fleischer, J.; Becker, J.
2023. Procedia CIRP, 120, 601–606. doi:10.1016/j.procir.2023.09.045
EFFECT: An End-to-End Framework for Evaluating Strategies for Parallel AI Anomaly Detection
Stammler, M.; Höfer, J.; Kraus, D.; Schmidt, P.; Hotfilter, T.; Harbaum, T.; Becker, J.
2023. Procedia Computer Science, 222, 499 – 508. doi:10.1016/j.procs.2023.08.188
CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems
Kreß, F.; Sidorenko, V.; Schmidt, P.; Hoefer, J.; Hotfilter, T.; Walter, I.; Harbaum, T.; Becker, J.
2023. Computer Networks, 229, Article no: 109759. doi:10.1016/j.comnet.2023.109759
Evaluation of GBT-FPGA for timing and fast control in CBM experiment
Sidorenko, V.; Müller, W. F. J.; Zabolotny, W.; Fröhlich, I.; Emschermann, D.; Becker, J.
2023. Journal of Instrumentation, 18 (2), Art.-Nr.: C02052. doi:10.1088/1748-0221/18/02/C02052
Operation of the Neural z-Vertex Track Trigger for Belle II in 2021 - a Hardware Perspective
Unger, K. L.; Bähr, S.; Becker, J.; Knoll, A. C.; Kiesling, C.; Meggendorfer, F.; Skambraks, S.
2023. Journal of Physics: Conference Series, 2438, Article no: 012056. doi:10.1088/1742-6596/2438/1/012056
Data-driven design of the Belle II track segment finder
Unger, K. L.; Neu, M.; Becker, J.; Schmidt, E.; Kiesling, C.; Meggendorfer, F.; Skambraks, S.
2023. Journal of Instrumentation, 18 (2), Art.-Nr.: C02001. doi:10.1088/1748-0221/18/02/C02001
Proceedingsbeiträge
The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective
Kempf, F.; Hoefer, J.; Harbaum, T.; Becker, J.; Fasfous, N.; Frickenstein, A.; Voegel, H.-J.; Friedrich, S.; Wittig, R.; Matúš, E.; Fettweis, G.; Lueders, M.; Blume, H.; Benndorf, J.; Grantz, D.; Zeller, M.; Engelke, D.; Eickel, K.-H.
2023. 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 17-19 April 2023, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE56975.2023.10137257
ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT Applications
Kreß, F.; Serdyuk, A.; Hiegle, M.; Waldmann, D.; Hotfilter, T.; Hoefer, J.; Hamann, T.; Barth, J.; Kämpf, P.; Harbaum, T.; Becker, J.
2023. 26th Euromicro Conference on Digital System Design (DSD 2023), 569–576, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD60849.2023.00084
Reinforcement Learning Enabled Multi-Layered NoC for Mixed Criticality Systems
Anantharajaiah, N.; Lesniak, F.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 38 – 44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00014
A Low-Stall Methodology for an Interleaved Processor State Replication
Kempf, F.; Höfer, J.; Hotfilter, T.; Becker, J.
2023. 2023 IEEE 16th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), 276 – 283, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC60832.2023.00048
Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing
Fürst-Walter, I.; Nappi, A.; Harbaum, T.; Becker, J.
2023. 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), Detroit, Mi, 1st-5th October 2023, 10888 – 10893, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IROS55552.2023.10341256
Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture Design
Pfau, J.; Hernandez, J.; Reuter, M.; Hofmann, K.; Becker, J.
2023. 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), Aalborg, 31st October - 01st November 2023, 7 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS58970.2023.10305486
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency
Hotfilter, T.; Hoefer, J.; Merz, P.; Kreß, F.; Kempf, F.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 36th International System-on-Chip Conference (SOCC), Santa Clara, USA, 05-08 September 2023, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC58585.2023.10256738
Towards Hardware-Software Self-Adaptive Acceleration of Spiking Neural Networks on Reconfigurable Digital Hardware
Pachideh, B.; Zielke, C.; Nitzsche, S.; Becker, J.
2023. 2023 IEEE 36th International System-on-Chip Conference (SOCC), Santa Clara, USA, 05-08 September 2023, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC58585.2023.10257066
European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving System
Hofman, D.; Brcic, M.; Kovac, M.; Hotfilter, T.; Becker, J.; Reinhardt, D.; Grigorescu, S. M.; Stevens, R.; Vo, T. T.
2023. 2023 IEEE 36th International System-on-Chip Conference (SOCC), Santa Clara, USA, 05-08 September 2023, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC58585.2023.10257105
Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors
Lesniak, F.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 36th International System-on-Chip Conference (SOCC), Santa Clara, USA, 05-08 September 2023, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC58585.2023.10257090
Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing
Kreß, F.; Pfau, J.; Kempf, F.; Schmidt, P.; He, Z.; Harbaum, T.; Becker, J.
2023. 2023 IEEE Nordic Circuits and Systems Conference (NorCAS), 31st October - 1st November 2023, Aalborg, Denmark, 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS58970.2023.10305469
Potential of systematically generated training datasets on the accuracy and generalization of AI-based approaches for the automated identification of machine control signals
Gönnheimer, P.; Ströbel, R.; Roßkopf, A.; Dörflinger, R.; Walter, I.; Becker, J.; Fleischer, J.
2023. 16th CIRP Conference on Intelligent Computation in Manufacturing Engineering CIRP ICME ‘22, Italy. Hrsg.: R. Teti, D. D’Addona, 145 – 150, Elsevier. doi:10.1016/j.procir.2023.06.026
DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC
Anantharajaiah, N.; Xu, Y.; Lesniak, F.; Harbaum, T.; Becker, J.
2023. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI59464.2023.10238569
Broadband MIMO Testbed for the Development and Research on 6G
Nuss, B.; Groeschel, P.; Pfau, J.; Becker, J.; Vossiek, M.; Zwick, T.
2023. European Wireless 2022 ; 27th European Wireless Conference, Dresden, 19th - 21st September 2022, 89 – 91, VDE VERLAG GMBH
A Hardware-Aware Sampling Parameter Search for Efficient Probabilistic Object Detection
Hoefer, J.; Hotfilter, T.; Kreß, F.; Qiu, C.; Harbaum, T.; Becker, J.
2023. Computer Vision Systems – 14th International Conference, ICVS 2023, Vienna, Austria, September 27–29, 2023. Ed.: H. Christensen, 299–309, Springer Nature Switzerland. doi:10.1007/978-3-031-44137-0_25
Pattern-Based Information Flow Control for Safety-Critical On-Chip Systems
Dörr, T.; Schade, F.; Becker, J.
2023. Computer Safety, Reliability, and Security. Ed.: J. Guiochet, 181–195, Springer Nature Switzerland. doi:10.1007/978-3-031-40923-3_14
A Scalable and Cost-Efficient Antenna Testbed Using FPGA-Server Compound Structures for Prototyping 6G Applications
Neu, M.; Karle, C.; Nuss, B.; Groeschel, P.; Becker, J.
2023. 2023 19th International Conference on Distributed Computing in Smart Systems and the Internet of Things (DCOSS-IoT), 171–178, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DCOSS-IoT58021.2023.00039
A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs
Hotfilter, T.; Höfer, J.; Kreß, F.; Kempf, F.; Kraft, L.; Harbaum, T.; Becker, J.
2023. 2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS), 1–5, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/AICAS57966.2023.10168566
Design and Implementation of Staggered-SAR Azimuth-Processing
Marten, J. C.; Younis, M.; Krieger, G.; Pfau, J.; Unger, K.; Becker, J.
2023. 24th International Radar Symposium (IRS), Berlin, Germany, 24-26 May 2023, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/IRS57608.2023.10172405
A Unified SoC Lab Course: Combined Teaching of Mixed Signal Aspects, System Integration, Software Development and Documentation
Pfau, J.; Leys, R.; Neu, M.; Serdyuk, A.; Peric, I.; Becker, J.
2023. 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 5 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISCAS46773.2023.10181679
LETSCOPE: Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics
Chu, A.; Hermann, C. M.; Silz, J.; Pfau, J.; Barón, K. M.; Anantharajaiah, N.; Schmidt, P.; Hotfilter, T.; Xie, X.; Becker, J.; Kallfass, I.; Roth-Stielow, J.; Stork, W.
2023. IEEE EUROCON 2023 - 20th International Conference on Smart Technologies, 665–670, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/EUROCON56442.2023.10199076
Multilevel Security Model for Secure Information Flow Inside Software Components Employing Automated Code Generation
Stammler, M.; Hamann, M.; Becker, J.
2023. 2023 12th Mediterranean Conference on Embedded Computing (MECO), 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MECO58584.2023.10154914
ReLoDAQ: Resource-Efficient, Low-Overhead 200 Gbits −1 Data Acquisition System for 6G Prototyping
Karle, C.; Neu, M.; Pfau, J.; Sperling, J.; Becker, J.
2023. 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 08-11 May 2023, Marina Del Rey, CA, USA, 209, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FCCM57271.2023.00037
Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems
Kempf, F.; Becker, J.
2023. 2023 12th Mediterranean Conference on Embedded Computing (MECO), 1–5, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MECO58584.2023.10154986
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators
Hoefer, J.; Kempf, F.; Hotfilter, T.; Kreß, F.; Harbaum, T.; Becker, J.
2023. Proceedings of the Great Lakes Symposium on VLSI 2023, 287–292, Association for Computing Machinery (ACM). doi:10.1145/3583781.3590226
Policy-Based Task Allocation at Runtime for a Self-Adaptive Edge Computing Infrastructure
Betancourt, V. P.; Kirschner, M.; Kreutzer, M.; Becker, J.
2023. 2023 IEEE 15th International Symposium on Autonomous Decentralized System (ISADS), 8 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISADS56919.2023.10092022
Non-Intrusive Runtime Monitoring for Manycore Prototypes
Lesniak, F.; Anantharajaiah, N.; Harbaum, T.; Becker, J.
2023. RAPIDO ’23: Proceedings of the DroneSE and RAPIDO: System Engineering for constrained embedded systems, 31–38, Association for Computing Machinery (ACM). doi:10.1145/3579170.3579262
An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload
Hotfilter, T.; Schmidt, P.; Höfer, J.; Kreß, F.; Harbaum, T.; Becker, J.
2023. DroneSE and RAPIDO: System Engineering for constrained embedded systems, 73–78, Association for Computing Machinery (ACM). doi:10.1145/3579170.3579258
Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores
Sandmann, T.; Becker, J.
2023. 2022 25th Euromicro Conference on Digital System Design (DSD), 189–196, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD57027.2022.00034
Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems
Anantharajaiah, N.; Becker, J.
2023. 2022 25th Euromicro Conference on Digital System Design (DSD), 174–180, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD57027.2022.00032
A holistic hardware-software approach for fault-aware embedded systems
Kempf, F.; Kühbacher, C.; Mellwig, C.; Altmeyer, S.; Ungerer, T.; Becker, J.
2023. 2022 25th Euromicro Conference on Digital System Design (DSD), 704–711, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD57027.2022.00099
Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA
Kreß, F.; Hoefer, J.; Hotfilter, T.; Walter, I.; El Annabi, E. M.; Harbaum, T.; Becker, J.
2023. Machine Learning and Principles and Practice of Knowledge Discovery in Databases. Hrsg.: I. Koprinska. Pt. 1, 557–568, Springer International Publishing. doi:10.1007/978-3-031-23618-1_37
Dissertationen
Task Allokation für effiziente Edge Computing Systeme. Dissertation
Pazmino Betancourt, V. H.
2023. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000158306
Skalierbarkeit einer Szenarien- und Template-basierten Simulation von Elektrik/Elektronik-Architekturen in reaktiven Umgebungen. Dissertation
Neubauer, K.
2023, Januar 19. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000154624
2022
Zeitschriftenaufsätze
The impact of formulation of cost function in Task Mapping Problem on NoCs using bio-inspired based-metaheuristics
de Barros, J. B.; Anantharajaiah, N.; Ayala-Rincón, M.; Llanos, C. H.; Becker, J.
2022. Microprocessors and Microsystems, 94, Art.-Nr.: 104668. doi:10.1016/j.micpro.2022.104668
Prototype design of a timing and fast control system in the CBM experiment
Sidorenko, V.; Fröhlich, I.; Müller, W. F. J.; Emschermann, D.; Bähr, S.; Sturm, C.; Becker, J.
2022. Journal of Instrumentation, 17, Art.-Nr.: C05008. doi:10.1088/1748-0221/17/05/C05008
V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling
Pfau, J.; Zaki, P. W.; Becker, J.
2022. Journal of Signal Processing Systems, 94, 865–882. doi:10.1007/s11265-022-01786-z
Lifecycle Management of Automotive Safety-Critical Over the Air Updates: A Systems Approach
Guissouma, H.; Hohl, C. P.; Lesniak, F.; Schindewolf, M.; Becker, J.; Sax, E.
2022. IEEE Access, 10, 57696–57717. doi:10.1109/ACCESS.2022.3176879
Dynamic Partial Reconfiguration for Adaptive Sensor Integration in Highly Flexible Manufacturing Systems
Schade, F.; Karle, C.; Mühlbeier, E.; Gönnheimer, P.; Fleischer, J.; Becker, J.
2022. Procedia CIRP, 107, 1311–1316. doi:10.1016/j.procir.2022.05.150
Applications and Techniques for Fast Machine Learning in Science
Deiana, A. M.; Tran, N.; Agar, J.; Blott, M.; Di Guglielmo, G.; Duarte, J.; Harris, P.; Hauck, S.; Liu, M.; Neubauer, M. S.; Ngadiuba, J.; Ogrenci-Memik, S.; Pierini, M.; Aarrestad, T.; Bähr, S.; Becker, J.; Berthold, A.-S.; Bonventre, R. J.; Müller Bravo, T. E.; Diefenthaler, M.; u. a.
2022. Frontiers in Big Data, 5, Art.Nr. 787421. doi:10.3389/fdata.2022.787421
Combined analysis of Belle and Belle II data to determine the CKM angle ϕ3 using B+ → D(K0S h+h−)h+ decays
Belle 2 Collaboration; Belle Collaboration; Abudinén, F.; Aggarwal, L.; Ahmed, H.; Aihara, H.; Akopov, N.; Al Said, S.; Aloisio, A.; Anh Ky, N.; Asner, D. M.; Atmacan, H.; Aushev, V.; Ayad, R.; Babu, V.; Bacher, S.; Baehr, S.; Bahinipati, S.; Bambade, P.; Becker, J.; u. a.
2022. Journal of high energy physics, 2022 (2), Artikel-Nr.: 63. doi:10.1007/JHEP02(2022)063
Proceedingsbeiträge
Reconfiguring an RFET Based Differential Amplifier
Reuter, M.; Kramer, A.; Krauss, T.; Pfau, J.; Becker, J.; Hofmann, K.
2022. 2022 IEEE 40th Central America and Panama Convention (CONCAPAN), 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/CONCAPAN48024.2022.9997726
Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDAR
Dörr, T.; Schade, F.; Masing, L.; Becker, J.; Keramidas, G.; Antonopoulos, C. P.; Mavropoulos, M.; Kelefouras, V.; Voros, N.
2022. 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Nicosia, Cyprus, 04-06 July 2022, 369–370, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI54635.2022.00081
A Behavior Specification and Simulation Methodology for Embedded Real-Time Software
Dörr, T.; Schade, F.; Ahlbrecht, A.; Zaeske, W.; Masing, L.; Durak, U.; Becker, J.
2022. 2022 IEEE/ACM 26th International Symposium on Distributed Simulation and Real Time Applications (DS-RT), 151–159, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DS-RT55542.2022.9932069
Using Trace Data for Run-Time Optimization of Parallel Execution in Real-Time Multi-Core Systems
Schade, F.; Sandmann, T.; Becker, J.; Theiling, H.
2022. 2022 IEEE 28th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Taipei, Taiwan, 23-25 August 2022, 228–234, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/RTCSA55878.2022.00031
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors
Kempf, F.; Höfer, J.; Kreß, F.; Hotfilter, T.; Harbaum, T.; Becker, J.
2022. Conference Proceedings: 2022 IEEE 35th International System-on-Chip Conference (SOCC) Ed.: S. Sezer, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC56010.2022.9908110
Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development
Schade, F.; Dörr, T.; Becker, J.
2022. Conference Proceedings: 2022 IEEE 35th International System-on-Chip Conference (SOCC) Ed.: S. Sezer, 1–2, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC56010.2022.9908090
Comparison of Artificial and Spiking Neural Networks for Ambient-Assisted Living
Nitzsche, S.; Pachideh, B.; Neher, M.; Kreutzer, M.; Link, N.; Theurer, L.; Becker, J.
2022. Conference Proceedings: 2022 Smart Systems Integration (SSI), 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SSI56489.2022.9901412
Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA
Hotfilter, T.; Kreß, F.; Kempf, F.; Becker, J.; Baili, I.
2022. 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Nicosia, Cyprus, 04-06 July 2022, 371–372. doi:10.1109/ISVLSI54635.2022.00082
XANDAR: A holistic Cybersecurity Engineering Process for Safety-critical and Cyber-physical Systems
Siddiqui, F.; Khan, R.; Sezer, S.; McLaughlin, K.; Masing, L.; Dörr, T.; Schade, F.; Becker, J.; Ahlbrecht, A.; Zaeske, W.; Durak, U.; Adler, N.; Sailer, A.; Weber, R.; Wilhelm, T.; Nemeth, G.; Nemeth, G.; Morales, V.; Gomez, P.; Keramidas, G.; u. a.
2022. 2022 IEEE 95th Vehicular Technology Conference: (VTC2022-Spring): Proceedings ; 19–22 June 2022, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/VTC2022-Spring54318.2022.9860859
Hardware-aware Partitioning of Convolutional Neural Network Inference for Embedded AI Applications
Kreß, F.; Hoefer, J.; Hotfilter, T.; Walter, I.; Sidorenko, V.; Harbaum, T.; Becker, J.
2022. 18th International Conference on Distributed Computing in Sensor Systems (DCOSS), 133–140, IEEEXplore. doi:10.1109/DCOSS54816.2022.00034
Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen
Kreß, F.; Serdyuk, A.; Hotfilter, T.; Höfer, J.; Harbaum, T.; Becker, J.; Hamann, T.
2022. 2022 11th Mediterranean Conference on Embedded Computing (MECO). Ed.: IEEE, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MECO55406.2022.9797131
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators
Karle, C. M.; Kreutzer, M.; Pfau, J.; Becker, J.
2022. HEART2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba Japan, June 9 - 10, 2022, 33–41, Association for Computing Machinery (ACM). doi:10.1145/3535044.3535049
AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms
Fasfous, N.; Vemparala, M. R.; Frickenstein, A.; Valpreda, E.; Salihu, D.; Höfer, J.; Singh, A.; Nagaraja, N.-S.; Voegel, H.-J.; Vu Doan, N. A.; Martina, M.; Becker, J.; Stechele, W.
2022. Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022). Ed.: C. Bolchini, 238–243, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE54114.2022.9774574
XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems
Masing, L.; Dörr, T.; Schade, F.; Becker, J.; Keramidas, G.; Antonopoulos, C. P.; Mavropoulos, M.; Tiganourias, E.; Kelefouras, V.; Antonopoulos, K.; Voros, N.; Durak, U.; Ahlbrecht, A.; Zaeske, W.; Panagiotou, C.; Karadimas, D.; Adler, N.; Sailer, A.; Weber, R.; Wilhelm, T.; u. a.
2022. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 14-23 March 2022, 814–818, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE54114.2022.9774534
Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs
Hotfilter, T.; Kreß, F.; Kempf, F.; Becker, J.; Haro, J. M. De; Jiménez-González, D.; Moretó, M.; Álvarez, C.; Labarta, J.; Baili, I.
2022. 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 14-23 March 2022, 628–631, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE54114.2022.9774716
PREUNN: Protocol Reverse Engineering using Neural Networks
Kiechle, V.; Börsig, M.; Nitzsche, S.; Baumgart, I.; Becker, J.
2022. Proceedings of the 8th International Conference on Information Systems Security and Privacy. Ed.: P. Mori. Vol. 1, 345–356, SciTePress. doi:10.5220/0010813500003120
Embedded Face Recognition for Personalized Services in the Assistive Robotics
Walter, I.; Ney, J.; Hotfilter, T.; Rybalkin, V.; Hoefer, J.; Wehn, N.; Becker, J.
2022. Machine Learning and Principles and Practice of Knowledge Discovery in Databases – International Workshops of ECML PKDD 2021, Virtual Event, September 13-17, 2021, Proceedings, Part I. Ed.: M. Kamp, 339–350, Springer International Publishing. doi:10.1007/978-3-030-93736-2_26
Forschungsberichte/Preprints
Final Report Sino-German Industry 4.0 Factory Automation Platform
Albers, A.; Ovtcharova, J.; Becker, J.; Lanza, G.; Zhang, W.; Zhang, T.; Qiao, F.; Ma, Y.; Wang, J.; Wu, Z.; Ehrmann, C.; Gönnheimer, P.; Behrendt, M.; Mandel, C.; Stürmlinger, T.; Klippert, M.; Kimmig, A.; Schade, F.; Yang, S.; Heider, I.; u. a.
2022. (J. Fleischer, Hrsg.), Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000143693
Dissertationen
Real-Time Trace Decoding and Monitoring for Safety and Security in Embedded Systems. Dissertation
Wankler Hoppe, A.
2022, Juli 27. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000148789
Low-Latency Track Triggering in High-Energy Physics. Dissertation
Ardila Pérez, L. E.
2022, Mai 11. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000145595
2021
Zeitschriftenaufsätze
Wertstromkinematik – Produktionssysteme neu gedacht: Interdisziplinäres Forscherteam arbeitet an der Produktionstechnik der Zukunft (Teil 2)
Kimmig, A.; Schöck, M.; Mühlbeier, E.; Oexle, F.; Fleischer, J.; Bönsch, J.; Ovtcharova, J.; Hahn, J.; Grunwald, A.; Albers, A.; Rapp, S.; Hagenmeyer, V.; Scholz, S. G.; Schmidt, A.; Müller, T.; Becker, J.; Schade, F.; Beyerer, J.; Rehak, J.; Zwick, T.; u. a.
2021. Zeitschrift für wirtschaftlichen Fabrikbetrieb, 116 (12), 935–939. doi:10.1515/zwf-2021-0207
Investigating real-time control-flow error detection in hardware: How fast can we detect errors and take action?
Hoppe, A.; Kastensmidt, F. L.; Becker, J.
2021. Microelectronics Reliability, 126, Art.-Nr.: 114264. doi:10.1016/j.microrel.2021.114264
Model-based configuration of access protection units for multicore processors in embedded systems
Dörr, T.; Sandmann, T.; Becker, J.
2021. Microprocessors and microsystems, 87, Article no: 104377. doi:10.1016/j.micpro.2021.104377
Achieving cost-efficient fail-operational behavior based on inherent redundancy at the system level
Dörr, T.; Sandmann, T.; Friederich, P.; Leitner, A.; Becker, J.
2021. Microprocessors and microsystems, 87, Aricle no: 104380. doi:10.1016/j.micpro.2021.104380
Feasibility studies of conserved charge fluctuations in Au-Au collisions with CBM
CBM Collaboration; Samanta, S.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2021. Nuclear physics <Amsterdam> / A, 1005, Art.-Nr.: 121896. doi:10.1016/j.nuclphysa.2020.121896
Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis
Bannwart Perina, A.; Silitonga, A.; Becker, J.; Bonato, V.
2021. IEEE transactions on computers, 70 (12), 2070–2082. doi:10.1109/TC.2021.3112260
Utilizing and Extending Trusted Execution Environment in Heterogeneous SoCs for a Pay-Per-Device IP Licensing Scheme
Khan, N.; Nitzsche, S.; Lopez, A. G.; Becker, J.
2021. IEEE transactions on information forensics and security / Institute of Electrical and Electronics Engineers, 16, 2548–2563. doi:10.1109/TIFS.2021.3058777
CBM Collaboration
CBM Collaboration; Ablyazimov, T.; Adak, R. P.; Adler, A.; Agarwal, A.; Agarwal, K.; Ahammed, Z.; Ahmad, A.; Ahmad, F.; Ahmad, N.; Akindinov, A.; Akishin, P.; Akishina, V.; Al-Turany, M.; Alekseev, I.; Alexandrov, E.; Alexandrov, I.; Becker, M.; Becker, K.-H.; Becker, J.; u. a.
2021. Nuclear physics <Amsterdam> / A, 1005, Article no: 122089. doi:10.1016/S0375-9474(20)30414-0
A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow
Masing, L.; Lesniak, F.; Becker, J.
2021. IEEE embedded systems letters, 13 (1). doi:10.1109/LES.2020.2995084
From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology
Reuter, M.; Pfau, J.; Krauss, T. A.; Becker, J.; Hofmann, K.
2021. IEEE transactions on circuits and systems / 1, 68 (1), 114–125. doi:10.1109/TCSI.2020.3035889
Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores
Khan, N.; Castro-Godinez, J.; Xue, S.; Henkel, J.; Becker, J.
2021. IEEE transactions on very large scale integration (VLSI) systems, 29 (1), 38–50. doi:10.1109/TVLSI.2020.3023548
Proceedingsbeiträge
Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation
Neubauer, K.; Masing, L.; Mahl, M.; Becker, J.; Kramer, M.; Reichmann, C.
2021. Proceedings of the 2021 32nd International Workshop on Rapid System Prototyping: Shortening the Path from Specification to Prototype ; October 14, 2021, Virtual Conference, 29–35, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/RSP53691.2021.9806231
Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology
Pfau, J.; Reuter, M.; Hofmann, K.; Becker, J.
2021. 2020 International Conference on Field-Programmable Technology (ICFPT), Maui, HI, USA, 09-11 December 2020, 165–173, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICFPT51103.2020.00031
Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems
Anantharajaiah, N.; Knopf, F.; Becker, J.
2021. Proceedings 34th IEEE International System-on-Chip Conference (SOCC): September 14–17, 2021, Virtual. Ed.: G. Qu, 248–253, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC52499.2021.9739596
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips
Hotfilter, T.; Hoefer, J.; Kreß, F.; Kempf, F.; Becker, J.
2021. IEEE 34th International System-on-Chip Conference (SOCC), 14th-17th September 2021, Las Vegas, Nevada, USA, 83–88, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC52499.2021.9739212
Ultra-low Power Machinery Fault Detection Using Deep Neural Networks
Nitzsche, S.; Neher, M.; Dosky, S. von; Becker, J.
2021. Machine Learning and Principles and Practice of Knowledge Discovery in Databases: International Workshops of ECML PKDD 2021, Virtual Event, September 13-17, 2021, Proceedings, Part I. Ed.: M. Kamp, 390–396, Springer. doi:10.1007/978-3-030-93736-2_30
XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems
Becker, J.; Masing, L.; Dörr, T.; Schade, F.; Keramidas, G.; Antonopoulos, C. P.; Mavropoulos, M.; Tiganourias, E.; Kelefouras, V.; Antonopoulos, K.; Voros, N.; Durak, U.; Ahlbrecht, A.; Zaeske, W.; Panagiotou, C.; Karadimas, D.; Adler, N.; Sailer, A.; Weber, R.; Wilhelm, T.; u. a.
2021. Proceedings 2021 31st International Conference on Field-Programmable Logic and Applications: FPL 2021 ; Dresden, Germany, 30 August – 3 September 2021, 382–383, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPL53798.2021.00075
Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands
Fasfous, N.; Vemparala, M.-R.; Frickenstein, A.; Badawy, M.; Hundhausen, F.; Höfer, J.; Nagaraja, N.-S.; Unger, C.; Vögel, H.-J.; Becker, J.; Asfour, T.; Stechele, W.
2021. 2021 IEEE International Conference on Robotics and Automation (ICRA): 30 May – 5 June 2021, Xi’an, China, 13430–13437, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICRA48506.2021.9561045
HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC)
Silitonga, A.; Kiyak, Y.; Becker, J.
2021. 2021 IEEE 15th International Conference on Anti-counterfeiting, Security, and Identification (ASID), 122–128, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ASID52932.2021.9651483
Virtual Verification of E/E Architectures for Secure Automated Driving Functions
Neubauer, K.; Rumez, M.; Tremmel, H.; Hoppe, A.; Kriesten, R.; Nenninger, P.; Sax, E.; Becker, J.
2021. 2021 IEEE International Symposium on Systems Engineering (ISSE): 13 September - 13 October 2021, online, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISSE51541.2021.9582552
Evaluation of a Hypervisor-Based Smart Controller for Industry 4.0 Functions in Manufacturing
Schade, F.; Barton, D.; Fleischer, J.; Becker, J.
2021. 7th IEEE World Forum on Internet of Things (WF-IoT), 680–685, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/WF-IoT51360.2021.9595534
Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks
Dörr, T.; Sandmann, T.; Mohr, H.; Becker, J.
2021. 2021 24th Euromicro Conference on Digital System Design (DSD), 107–114, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD53832.2021.00026
An Adaptive Lockstep Architecture for Mixed-Criticality Systems
Kempf, F.; Hartmann, T.; Bähr, S.; Becker, J.
2021. 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI): 7-9 July 2021, Tampa, FL, USA, 7–12, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI51109.2021.00013
High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring
Hoppe, A.; Becker, J.; Kastensmidt, F. L.
2021. 2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS) : 12th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2021, Arequipa, 22 February 2021 - 25 February 2021, Art.-Nr.: 9459137, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/LASCAS51355.2021.9459137
Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA
Pfau, J.; Zaki, P. W.; Becker, J.
2021. Applied Reconfigurable Computing. Architectures, Tools, and Applications: 17th International Symposium, ARC 2021, Virtual Event, June 29–30, 2021, Proceedings. Ed.: S. Derrien, 35–49, Springer-Verlag. doi:10.1007/978-3-030-79025-7_3
Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems
Anantharajaiah, N.; Zhang, Z.; Becker, J.
2021. Applied Reconfigurable Computing. Ed.: S. Derrien, 125–139, Springer Nature Switzerland. doi:10.1007/978-3-030-79025-7_9
Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel Attacks
Khan, N.; Hettwer, B.; Becker, J.
2021. Applied Reconfigurable Computing. Ed.: S. Derrien, 188–202, Springer Nature Switzerland. doi:10.1007/978-3-030-79025-7_13
Transparent Near-Memory Computing with a Reconfigurable Processor
Lesniak, F.; Kreß, F.; Becker, J.
2021. Applied Reconfigurable Computing. Ed.: S. Derrien, 221–231, Springer Nature Switzerland. doi:10.1007/978-3-030-79025-7_15
Security-driven Cross-Layer Model & Description of a HW/SW Framework for AP MPSoC-based Computing Device
Silitonga, A.; Becker, J.
2021. The 14th IEEE International Systems Conference (SYSCON), Montreal, Canada (Virtual), 24-27 August, 2020, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SysCon47679.2020.9353653
Forschungsberichte/Preprints
Prototype design of a timing and fast control system in the CBM experiment
Sidorenko, V.; Fröhlich, I.; Müller, W. F. J.; Emschermann, D.; Bähr, S.; Sturm, C.; Becker, J.
2021. doi:10.48550/arXiv.2110.12738
Audio & Video
Institut für Technik der Informationverarbeitung: Institutsvorstellung
Becker, J.; Sax, E.; Stork, W.
2021
Dissertationen
Trusted SoC Realization for Remote Dynamic IP Integration. Dissertation
Khan, N. M.
2021, Dezember 16. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000140875
Dynamische Rekonfigurationsmethodik für zuverlässige, echtzeitfähige Eingebettete Systeme in Automotive. Dissertation
Oszwald, F.
2021, Oktober 12. KIT Scientific Publishing. doi:10.5445/KSP/1000132321
2020
Zeitschriftenaufsätze
Transverse and longitudinal segmented forward hadron calorimeters with SiPMs light readout for future fixed target heavy ion experiments
BM@N Collaboration; CBM Collaboration; NA61/SHINE Collaboration; Guber, F.; Finogeev, D.; Golubeva, M.; Ivashkin, A.; Izvestnyy, A.; Karpushkin, N.; Morozov, S.; Kugler, A.; Mikhaylov, V.; Senger, A.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; u. a.
2020. Nuclear instruments & methods in physics research / A, 958, Art.-Nr. 162728. doi:10.1016/j.nima.2019.162728
Status of the Compressed Baryonic Matter experiment at FAIR
CBM Collaboration; Senger, P.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2020. International journal of modern physics / E, 29 (02), 2030001–1. doi:10.1142/S0218301320300015
Probing dense QCD matter in the laboratory—The CBM experiment at FAIR
CBM Collaboration; Senger, P.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2020. Physica scripta, 95 (7), Art.-Nr.: 074003. doi:10.1088/1402-4896/ab8c14
Physics Performance Studies for Anisotropic Flow Measurements with the CBM Experiment at FAIR
CBM Collaboration; Golosov, O.; Klochkov, V.; Kashirin, E.; Selyuzhenkov, I.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2020. Physics of particles and nuclei, 51 (3), 297–300. doi:10.1134/S1063779620030119
Using multiplicity of produced particles for centrality determination in heavy-ion collisions with the CBM experiment
CBM Collaboration; Segal, I.; Lubynets, O.; Selyuzhenkov, I.; Klochkov, V.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2020. Journal of Physics: Conference Series, 1690, Art.-Nr.: 012107. doi:10.1088/1742-6596/1690/1/012107
Performance for proton anisotropic flow measurement of the CBM experiment at FAIR
CBM Collaboration; Golosov, O.; Klochkov, V.; Kashirin, E.; Selyuzhenkov, I.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2020. Journal of Physics: Conference Series, 1690, Art.-Nr. 012104. doi:10.1088/1742-6596/1690/1/012104
Search for Axionlike Particles Produced in e⁺ e⁻ Collisions at Belle II
Belle 2 Collaboration; Abudinén, F.; Adachi, I.; Aihara, H.; Akopov, N.; Aloisio, A.; Ameli, F.; Anh Ky, N.; Asner, D. M.; Aushev, T.; Aushev, V.; Babu, V.; Baehr, S.; Bahinipati, S.; Bambade, P.; Banerjee, S.; Bansal, S.; Baudot, J.; Becker, J.; Behera, P. K.; u. a.
2020. Physical review letters, 125 (16), Article: 161806. doi:10.1103/PhysRevLett.125.161806
A 3D track finder for the Belle II CDC L1 trigger
Skambraks, S.; Bähr, S.; Becker, J.; Kiesling, C.; McCarney, S.; Meggendorfer, F.; Tonder, R. V.; Lukas Unger, K.
2020. Journal of physics / Conference series, 1525 (1), Art. Nr.: 012102. doi:10.1088/1742-6596/1525/1/012102
Search for an Invisibly Decaying Z’ Boson at Belle II in e⁺e⁻ → μ⁺μ⁻(eμ) Plus Missing Energy Final States
Belle 2 Collaboration; Adachi, I.; Ahlburg, P.; Aihara, H.; Akopov, N.; Aloisio, A.; Anh Ky, N.; Asner, D. M.; Atmacan, H.; Aushev, T.; Aushev, V.; Aziz, T.; Babu, V.; Baehr, S.; Bambade, P.; Banerjee, S.; Bansal, V.; Barrett, M.; Baudot, J.; Becker, J.; u. a.
2020. Physical review letters, 124 (14), Article: 141801. doi:10.1103/PhysRevLett.124.141801
Measurement of the integrated luminosity of the Phase 2 data of the Belle II experiment
Belle 2 Collaboration; Abudinén, F.; Adachi, I.; Ahlburg, P.; Aihara, H.; Akopov, N.; Aloisio, A.; Ameli, F.; Andricek, L.; Anh Ky, N.; Asner, D. M.; Atmacan, H.; Aushev, T.; Aushev, V.; Aziz, T.; Azmi, K.; Babu, V.; Baehr, S.; Bahinipati, S.; Becker, J.; u. a.
2020. Chinese physics / C, 44 (2), Article: 021001. doi:10.1088/1674-1137/44/2/021001
Proceedingsbeiträge
Fine Grained Control Flow Checking with Dedicated FPGA Monitors
Hoppe, A.; Becker, J.; Kastensmidt, F. L.
2020. 2020 IEEE 33rd International System-on-Chip Conference (SOCC): 8-11 September 2020, Las Vegas, NV, USA (online), 219–224, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC49529.2020.9524751
Fuzzing Framework for ESP32 Microcontrollers
Borsig, M.; Nitzsche, S.; Eisele, M.; Gröll, R.; Becker, J.; Baumgart, I.
2020. 2020 IEEE International Workshop on Information Forensics and Security (WIFS), 6-11 December 2020, online, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/WIFS49906.2020.9360889
A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCs
Barros, J. B. de; Anantharajaiah, N.; Ayala-Rincon, M.; Llanos, C. H.; Becker, J.
2020. 2020 IEEE Nordic Circuits and Systems Conference (NorCAS), 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NorCAS51424.2020.9265134
Towards an On-Demand Redundancy Concept for Autonomous Vehicle Functions using Microservice Architecture
Liu, B.; Betancourt, V. P.; Zhu, Y.; Becker, J.
2020. 2020 IEEE International Symposium on Systems Engineering (ISSE), Article no: 9272016, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISSE49799.2020.9272016
An Architecture-based Modeling Approach Using Data Flows for Zone Concepts in Industry 4.0
Kern, M.; Taspolatoglu, E.; Scheytt, F.; Glock, T.; Liu, B.; Betancourt, V. P.; Becker, J.; Sax, E.
2020. 6th IEEE International Symposium on Systems Engineering (ISSE 2020), Vienna, A, 12 October - 12 November 2020, Article no: 9272013, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISSE49799.2020.9272013
Model-based Development of a Dynamic Container-Based Edge Computing System
Betancourt, V. P.; Liu, B.; Becker, J.
2020. 2020 IEEE International Symposium on Systems Engineering (ISSE), 1–5, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISSE49799.2020.9272014
Linking Intrusion Detection System Information and System Model to Redesign Security Architecture
Betancourt, V. P.; Glock, T.; Kharitonov, A.; Kern, M.; Liu, B.; Sax, E.; Becker, J.
2020. 2020 IEEE International Systems Conference (SysCon), 1–7, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SysCon47679.2020.9275862
QUA³CK - A Machine Learning Development Process
Stock, S. C.; Becker, J.; Grimm, D.; Hotfilter, T.; Molinar, G.; Stang, M.; Stork, W.
2020. Proceedings of Artificial Intelligence for Science, Industry and Society — PoS(AISIS2019), 026, Scuola Internazionale Superiore di Studi Avanzati (SISSA). doi:10.22323/1.372.0026
Online Estimation of Particle Track Parameters based on Neural Networks for the Belle II Trigger System
Baehr, S.; Unger, K. L.; Becker, J.; Meggendorfer, F.; Skambraks, S.; Kiesling, C.
2020. Proceedings of Artificial Intelligence for Science, Industry and Society — PoS(AISIS2019), 010, Scuola Internazionale Superiore di Studi Avanzati (SISSA). doi:10.22323/1.372.0010
MiteS: Software-based Microarchitectural Attacks and Countermeasures in networked AP SoC Platforms
Silitonga, A.; Gassoumi, H.; Becker, J.
2020. The 14th IEEE International Conference on Anti-counterfeiting, Security, and Identification (ASID), Xiamen, China (Virtual), Oct. 31-Nov. 1, 2020, 65–71, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ASID50160.2020.9271734
An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems
Dörr, T.; Sandmann, T.; Friederich, P.; Leitner, A.; Becker, J.
2020. 2020 23rd Euromicro Conference on Digital System Design (DSD), 630–637, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD51259.2020.00103
A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems
Dörr, T.; Sandmann, T.; Becker, J.
2020. 2020 23rd Euromicro Conference on Digital System Design (DSD), 596–603, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD51259.2020.00098
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s
Pfau, J.; Reuter, M.; Harbaum, T.; Hofmann, K.; Becker, J.
2020. 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 3-6 Sept. 2019, 294–299, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570548289
Observation of a Charged Charmoniumlike Structure in e+e−→π+π−J/ψ at s√=4.26 GeV
Ablikim, M.; Achasov, M. N.; Ai, X. C.; Albayrak, O.; Ambrose, D. J.; An, F. F.; An, Q.; Bai, J. Z.; Ferroli, R. B.; Ban, Y.; Becker, J.; Bennett, J. V.; Bertani, M.; Bian, J. M.; Boger, E.; Bondarenko, O.; Boyko, I.; Briere, R. A.; Bytev, V.; Cai, H.; u. a.
2020. 30 Years of Bes Physics : Proceedings of the Symposium on 30 Years of Bes Physics. Ed.: editet M. Ye, 229–235, World Scientific Publishing. doi:10.1142/9789811217739_0033
Observation of a Charged Charmoniumlike Structure Zc(4020) and Search for the Zc(3900) in e+e−→π+π−hc
Ablikim, M.; Achasov, M. N.; Albayrak, O.; Ambrose, D. J.; An, F. F.; An, Q.; Bai, J. Z.; Ferroli, R. B.; Ban, Y.; Becker, J.; Bennett, J. V.; Bertani, M.; Bian, J. M.; Boger, E.; Bondarenko, O.; Boyko, I.; Braun, S.; Briere, R. A.; Bytev, V.; Cai, H.; u. a.
2020. 30 Years of Bes Physics : Proceedings of the Symposium on 30 Years of Bes Physics. Ed.: M. Ye, 236–242, World Scientific Publishing. doi:10.1142/9789811217739_0034
Model Driven Development Process for a Service-oriented Industry 4.0 System
Liu, B.; Glock, T.; Betancourt, V. P.; Kern, M.; Sax, E.; Becker, J.
2020. 2020 9th International Conference on Industrial Technology and Management (ICITM), 78–83, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICITM48982.2020.9080344
Model-Based Development and Simulative Verification of Logical Vehicle Functions Using Executable UN/ECE Regulations
Neubauer, K.; Bucher, H.; Haas, B.; Becker, J.
2020. Proceedings of the 2020 Summer Simulation Conference, Society for Computer Simulation International, San Diego, CA, United States, Art.-Nr.: 31, Association for Computing Machinery (ACM)
Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications
Reuter, M.; Pfau, J.; Krauss, T. A.; Moradinasab, M.; Schwalke, U.; Becker, J.; Hofmann, K.
2020. Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems (LASCAS), San Jose, Costa Rica, February 15-28, 2020, Article No. 9069043, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/LASCAS45839.2020.9069043
WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers
Reder, S.; Becker, J.
2020. 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, France, 9-13 March 2020, 210–215, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE48585.2020.9116400
Embedded Image Processing the European Way: A new platform for the future automotive market
Hotfilter, T.; Kempf, F.; Becker, J.; Reinhardt, D.; Baili, I.
2020. 6th IEEE World Forum on Internet of Things, WF-IoT 2020, New Orleans, United States, 2 - 16 June 2020, Art.Nr. 9221396, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/WF-IoT48130.2020.9221396
Interference-Aware Memory Allocation for Real-Time Multi-Core Systems
Reder, S.; Becker, J.
2020. 26th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 148–159, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/RTAS48715.2020.00-10
Realization of a state machine based detection for Track Segments in the Trigger System of the Belle II Experiment
Unger, K. L.; Bähr, S.; Becker, J.; Iwasaki, Y.; Kim, K.; Lai, Y.-T.
2020. Proceedings of Topical Workshop on Electronics for Particle Physics, TWEPP 2019, Santiago de Compostela, Spain, 2 - 6 September 2019, Code 160323. doi:10.22323/1.370.0145
Model-Based Design of Service-Oriented Architectures for Reliable Dynamic Reconfiguration
Oszwald, F.; Obergfell, P.; Liu, B. B.; Victor Pazmino; Becker, J.
2020. WCX 2020 SAE World Congress Experience, Detroit, MI, April 21-23, 2020. Proceedings. doi:10.4271/2020-01-1364
Evaluation Methodologies in the Development of Dynamically Reconfigurable Systems in the Automotive Industry
Oszwald, F.; Bertelo, R.; Gericota, M.; Becker, J.
2020. WCX SAE World Congress Experience, Detroit, MI, April 21-23, 2020. Proceedings. doi:10.4271/2020-01-1363
Dissertationen
Integrierte modell- und simulationsbasierte Entwicklung zur dynamischen Bewertung automobiler Elektrik/Elektronik-Architekturen. Dissertation
Bucher, H.
2020, Dezember 1. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000126919
Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures. Dissertation
Masing, L. J.
2020, November 26. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000126812
Compileroptimierung und parallele Code-Generierung für zeitkritische eingebettete Multiprozessorsysteme. Dissertation
Reder, S. T.
2020, Oktober 7. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000124294
2019
Zeitschriftenaufsätze
The very forward hadron calorimeter PSD for the future CBM@FAIR experiment
CBM Collaboration; Mikhaylov, V.; Kugler, A.; Kushpil, V.; Svoboda, O.; Tlustý, P.; Golubeva, M.; Guber, F.; Ivashkin, A.; Morozov, S.; Klochkov, V.; Selyuzhenkov, I.; Senger, A.; Bondarenko, S.; Burov, V.; Malakhov, A.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; u. a.
2019. The European physical journal / Web of Conferences, 204, Art.-Nr.: 11004. doi:10.1051/epjconf/201920411004
The Projectile Spectator Detector for measuring the geometry of heavy ion collisions at the CBM experiment on FAIR
CBM Collaboration; Karpushkin, N.; Finogeev, D.; Golubeva, M.; Guber, F.; Ivashkin, A.; Izvestnyy, A.; Ladygin, V.; Morozov, S.; Kugler, A.; Mikhaylov, V.; Senger, A.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; u. a.
2019. Nuclear instruments & methods in physics research / A, 936, 156–157. doi:10.1016/j.nima.2018.10.054
Exploring Cosmic Matter in the Laboratory—The Compressed Baryonic Matter Experiment at FAIR
CBM Collaboration; Senger, P.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2019. Particles, 2 (4), 499–510. doi:10.3390/particles2040031
An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter
Figuli, S. P. D.; Becker, J.
2019. Journal of circuits, systems, and computers, 28 (1), Art. Nr.: 1950015. doi:10.1142/S0218126619500154
Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications
Reder, S.; Kempf, F.; Bucher, H.; Becker, J.; Alefragis, P.; Voros, N.; Skalistis, S.; Derrien, S.; Puaut, I.; Oey, O.; Stripf, T.; Ferdinand, C.; David, C.; Ulbig, P.; Mueller, D.; Durak, U.
2019. Journal of aerospace information systems, 16 (11), 521–533. doi:10.2514/1.I010749
Methodical approach for the development of a platform for the configuration and operation of turnkey production systems
Gönnheimer, P.; Kimmig, A.; Mandel, C.; Stürmlinger, T.; Yang, S.; Schade, F.; Ehrmann, C.; Klee, B.; Behrendt, M.; Schlechtendahl, J.; Fischer, M.; Trautmann, K.; Fleischer, J.; Lanza, G.; Ovtcharova, J.; Becker, J.; Albers, A.
2019. Procedia CIRP, 84, 880–885. doi:10.1016/j.procir.2019.04.260
Evaluation of a high-throughput communication link for future automotive ADAS controllers
Yigui, L.; Youteng, S.; Schade, F.; Hotfilter, T.; Becker, J.; Yuan, Z.; Zizhou, O.; Weiming, L.
2019. Proceedings of the Institution of Mechanical Engineers / D, 233 (9), 2371–2378. doi:10.1177/0954407019851334
Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II
Bucher, H.; Kamm, S.; Becker, J.
2019. Simulation Notes Europe, 29 (2), 73–78. doi:10.11128/sne.29.tn.10472
Modular smart controller for Industry 4.0 functions in machine tools
Barton, D.; Gönnheimer, P.; Schade, F.; Ehrmann, C.; Becker, J.; Fleischer, J.
2019. Procedia CIRP, 81, 1331–1336. doi:10.1016/j.procir.2019.04.022
Proceedingsbeiträge
Establishing and Enhancing Agility with Model-based Systems Engineering
Oszwald, F.; Obergfell, P.; Meseth, M.; Chamas, M.; Traub, M.; Becker, J.; Sax, E.
2019. Proceedings of the 19th International Congress Electronics in Vehicles (ELIV), 16. - 17. Oktober 2019
A Network on Chip Adapter for Real-Time and Safety-Critical Applications
Kempf, F.; Anantharajaiah, N.; Masing, L.; Becker, J.
2019. 32nd IEEE International System on Chip Conference, SOCC 2019; Singapore; Singapore; 3 September 2019 through 6 September 2019. Ed.: D. Zhao, 39–44, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570558594
Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration
Oszwald, F.; Obergfell, P.; Traub, M.; Becker, J.
2019. 32nd IEEE International System on Chip Conference, SOCC 2019; Singapore; Singapore; 3 September 2019 through 6 September 2019. Ed.: D. Zhao, 203–208, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC46988.2019.1570547977
Lina: Timing-constrained high-level synthesis performance estimator for fast DSE
Bannwart Perina, A.; Becker, J.; Bonato, V.
2019. 2019 International Conference on Field-Programmable Technology : ICFPT 2019 : Tianjin, China, 9-13 December 2019 : proceedings, 343–346, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICFPT47387.2019.00063
ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis
Perina, A. B.; Becker, J.; Bonato, V.
2019. 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2019), 618–621, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICECS46596.2019.8964669
From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI
Reuter, M.; Krauss, T. A.; Moradinasab, M.; Pfau, J.; Schwalke, U.; Becker, J.; Hofmann, K.
2019. Proceedings. 2019 IEEE Asia Pacific Conference on Circuits and Systems : Royal Orchind Sheraton Hotel and Towers Bangkok, Thailand, November 11-14, 2019, 113–116, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/APCCAS47518.2019.8953083
Dynamic and scalable runtime block-based multicast routing for networks on chips
Anantharajaiah, N.; Kempf, F.; Masing, L.; Lesniak, F. M.; Becker, J.
2019. Proceedings of the 12th International Workshop on Network on Chip Architectures (NoCArc 2019), Columbus, OH, Ocober 12-13, 2019, 1–6, Association for Computing Machinery (ACM). doi:10.1145/3356045.3360718
Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs
Silitonga, A.; Jiang, Z.; Khan, N.; Becker, J.
2019. 2019 IEEE Nordic Circuits and Systems Conference (NorCAS), Helsinki, FIN, October 29-30, 2019, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NORCHIP.2019.8906923
Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II : [extended version]
Bucher, H.; Kamm, S.; Becker, J.
2019. Proceedings of the 51st Summer Computer Simulation Conference, SummerSim 2019, ACM, Art.-Nr. 18, Society for Computer Simulation International. doi:10.5555/3374138.3374156
Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration [in press]
Oszwald, F.; Obergfell, P.; Traub, M.; Becker, J.
2019. Proceedings of the 32nd IEEE International System-on-Chip Conference (SOCC), Singapur, 3 - 6 September 2019
Model-Driven Design of Tools for Multi-Domain Systems with Loosely Coupled Metamodels [in press]
Liu, B.; Glock, T.; Sax, E.; Pazmino Betancourt, V.; Kern, M.; Becker, J.
2019. Annual IEEE International Systems Conference, Orlando, USA, 8 - 11 April 2019
Low Latency Neural Networks using Heterogenous Resources on FPGA for the Belle II Trigger
Baehr, S.; Poehler, J.; Unger, K.; Hochstuhl, A.; Becker, J.; Skambraks, S.; McCarney, S.; Meggendorfer, F.; Kiesling, C.
2019. Connecting the Dots and Workshop on Intelligent Trackers (CTD/WIT 2019), València, E, April 2-5, 2019
A secure framework with remote configuration of intellectual property
Khan, N.; Nitzsche, S.; Becker, J.
2019. 5th International Conference on Information Systems Security and Privacy, ICISSP 2019; Prague; Czech Republic; 23 February 2019 through 25 February 2019. Ed.: P. Mori, 564–571, SciTePress. doi:10.5220/0007576305640571
Hybrid Prototyping for Manycore Design and Validation
Masing, L.; Lesniak, F.; Becker, J.
2019. 15th International Symposium on Applied Reconfigurable Computing, ARC 2019; Darmstadt; Germany; 9 April 2019 through 11 April 2019, 319–333. doi:10.1007/978-3-030-17227-5_23
Secure Local Configuration of Intellectual Property Without a Trusted Third Party
Khan, N.; Silitonga, A.; Pachideh, B.; Nitzsche, S.; Becker, J.
2019. Applied reconfigurable computing : 15th international symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019 : proceedings, 137–146, Springer. doi:10.1007/978-3-030-17227-5_11
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems
Dörr, T.; Sandmann, T.; Schade, F.; Bapp, F. K.; Becker, J.
2019. Applied Reconfigurable Computing – 15th International Symposium, ARC 2019, Darmstadt, 9.-11. April 2019, 96–111, Springer. doi:10.1007/978-3-030-17227-5_8
Service-Based Industry 4.0 Middleware for Partly Automated Collaborative Work of Cranes
Glock, T.; Betancourt, V. P.; Kern, M.; Liu, B.; Reiß, T.; Sax, E.; Becker, J.
2019. 8th International Conference on Industrial Technology and Management (ICITM 2019), Cambridge, UK, March 2-4, 2019
Automated Assessment of E/E-Architecture Variants Using an Integrated Model- and Simulation-Based Approach
Bucher, H.; Neubauer, K.; Becker, J.
2019. WCX SAE World Congress Experience, Detroit, USA, April 9-11 2019, 14 S., SAE International. doi:10.4271/2019-01-0111
Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II
Bucher, H.; Kamm, S.; Becker, J.
2019. ASIM-Workshop Simulation Technischer Systeme / Grundlagen und Methoden in Modellbildung und Simulation, Braunschweig, Germany, 21. Februar 2019 - 22. Februar 2019. Ed.: U. Durak, 7–12, ARGESIM. doi:10.11128/arep.57
Forschungsberichte/Preprints
Measurement of the integrated luminosity of the Phase 2 data of the Belle II experiment
Belle 2 Collaboration; Bähr, S.; Becker, J.; Unger, K.
2019
Vorträge
The QUA³CK Machine Learning Development Process and the Laboratory for Applied Machine Learning Approaches (LAMA)
Becker, J.; Grimm, D.; Hotfilter, T.; Meier, C.; Molinar, G.; Stang, M.; Stock, S.; Stork, W.
2019, Oktober 22. Symposium Artificial Intelligence for Science, Industry and Society (AISIS 2019), Mexiko-Stadt, Mexiko, 20. Oktober–25. Dezember 2019
Dissertationen
Dynamisch adaptive Mikroarchitekturen mit optimierten Speicherstrukturen und variablen Befehlssätzen. Dissertation
Harbaum, T.
2019. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000096122
2018
Buchaufsätze
Advances in Avionic Platforms : Multi-Core Systems
Bapp, F.; Becker, J.
2018. Advances in Aeronautical Informatics : Technologies Towards Flight 4.0. Ed.: U. Durak, 17–27, Springer. doi:10.1007/978-3-319-75058-3_2
Bücher
Advances in Aeronautical Informatics
Durak, U. D.; Becker, J.; Hartmann, S.; Voros, N. S.
2018. Springer International Publishing. doi:10.1007/978-3-319-75058-3
Zeitschriftenaufsätze
Event Topology Reconstruction in the CBM Experiment
CBM Collaboration; Kisel, I.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2018. Journal of Physics: Conference Series, 1070, 012015. doi:10.1088/1742-6596/1070/1/012015
OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures
Sotiriou-Xanthopoulos, E.; Masing, L.; Xydis, S.; Siozios, K.; Becker, J.; Soudris, D.
2018. ACM transactions on embedded computing systems, 17 (5), Article: 86. doi:10.1145/3242179
Proceedingsbeiträge
Using simulation techniques within the design of a reconfigurable architecture for fail-operational real-time automotive embedded systems
Oszwald, F.; Obergfell, P.; Traub, M.; Becker, J.
2018. 4th IEEE International Symposium on Systems Engineering, ISSE 2018; Rome Marriott Park HotelRoma; Italy; 1 October 2018 through 3 October 2018, Art. Nr.: 8544451, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SysEng.2018.8544451
HLS-based Performance and Resource Optimization of Cryptographic Modules
Silitonga, A.; Schade, F.; Jiang, G.; Becker, J.
2018. Proceedings of the 16th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA2018), Melbourne, Australia, 11th-13th December 2018, 1009–1016, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/BDCloud.2018.00147
RAW 2018 Invited Talks
Becker, J.; Prasanna, V. K.; Weimer, M.; Luk, W.; Aasaraai, K.; Chiou, D.
2018. 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Vancouver, CDN, May 21-25, 2018, 81–82, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IPDPSW.2018.00021
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. IEEE 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Hanoi, VN, September 12-14, 2018, 138–145, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC2018.2018.00033
Modellbasiertes Entwicklungswerkzeug für den Entwurf und die Analyse von angriffsresistenten Industrie 4.0 Systemen
Betancourt, V. P.; Glock, T.; Kern, M.; Sax, E.; Becker, J.
2018. VDI Automation 2018 - 19. Leitkongress der Mess- und Automatisierungstechnik Seamless Convergence of Automation & IT, Baden-Baden, 03.-04. Juli 2018, embeX GmbH
Dynamic reconfiguration for real-time automotive embedded systems in fail-operational context
Oszwald, F.; Becker, J.; Obergfell, P.; Traub, M.
2018. 32nd IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2018; Vancouver; Canada; 21 May 2018 through 25 May 2018, 206–209, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IPDPSW.2018.00039
Data Reduction and Readout Triggering in Particle Physics Experiments Using Neural Networks on FPGAs
Baehr, S.; Kempf, F.; Becker, J.
2018. Proceedings of the 18th International Conference on Nanotechnology (IEEE-NANO 2018), Cork, IRL, July 23-26, 2018, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NANO.2018.8626239
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks
Baehr, S.; Kempf, F.; Becker, J.
2018. Proceedings of the 31th IEEE International System-on-Chip Conference (SOCC), Arlington, VA, September 4-7, 2018, 174–179, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2018.8618563
A Content-Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique
Harbaum, T.; Balzer, M.; Becker, J.; Weber, M.
2018. Proceedings of the 31th IEEE International System-on-Chip Conference (SOCC), 118–123, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2018.8618493
Electric Circuit- and Wiring Harness-Aware Behavioral Simulation of Model-Based E/E-Architectures at System Level
Bucher, H.; Becker, J.
2018. IEEE International Systems Engineering Symposium (ISSE), Rome, I, October 1-3, 2018, 1–8, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SysEng.2018.8544434
Mapping and Scheduling Hard Real Time Applications on Multicore Systems : The ARGO Approach
Alefragis, P.; Theodoridis, G.; Katsimpris, M.; Valouxis, C.; Gogos, C.; Goulas, G.; Voros, N.; Reder, S.; Kasnakli, K.; Bednara, M.; Müller, D.; Durak, U.; Becker, J.
2018. Applied Reconfigurable Computing - Architectures, Tools, and Applications, Proceedings of the 14th International Symposium, ARC 2018, Santorini, Greece, 2nd - 4th May 2018. Ed.: C. Antonopoulos, 700–711, Springer. doi:10.1007/978-3-319-78890-6_56
The ARAMiS Project Initiative : Multicore Systems in Safety- and Mixed-Critical Applications
Becker, J.; Bapp, F. K.
2018. Applied Reconfigurable Computing - Architectures, Tools, and Applications, Proceedings of the 14th International Symposium, ARC 2018, Santorini, Greece, 2nd - 4th May 2018. Ed.: G. Keramidas, 685–699, Springer. doi:10.1007/978-3-319-78890-6_55
Scenario-based development of an industry 4.0 domain description language for a plant architecture
Glock, T.; Groß, T.; Kern, M.; Betancourt, V. P.; Sax, E.; Becker, J.
2018. 7th International Conference on Industrial Technology and Management (ICITM), Oxford, UK, March 7-9, 2018, 71–77, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICITM.2018.8333922
Interactive Parallelization of Embedded Real-Time Applications Starting from Open-Source Scilab and Xcos
Oey Oliver; Rückauer, M.; Stripf, T.; Becker, J.; David, C.; Debray, Y.; Müller, D.; Durak, U.; Kasnakli, E. K.; Bednara, M.; Schöberl, M.
2018. 9th European Congress - Embedded Real Time Software and Systems - ERTS² 2018, Toulouse, F, January 31- February 2, 2018
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems
Pfau, J.; Figuli, S. P. D.; Bähr, S.; Becker, J.
2018. Applied Reconfigurable Computing - Architectures, Tools, and Applications, Proceedings of the 14th International Symposium, ARC 2018, Santorini, Greece, 2nd - 4th May 2018. Ed.: Nikolaos Voros, 615–626, Springer. doi:10.1007/978-3-319-78890-6_49
A WCET-Aware Parallel Programming Model for Predictability Enhanced Multi-core Architectures
Reder, S.; Masing, L.; Bucher, H.; Braak, T. ter; Stripf, T.; Becker, J.
2018. Proceedings of the 2018 Design, Automation & Test in Europe (DATE) : 19-23 March 2018, Dresden, Germany. Ed. J. Madsen, 943–948, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE.2018.8342145
Control Flow Analysis for Embedded Multi-Core Hybrid Systems
Hoppe, A. W.; Kastensmidt, F. L.; Becker, J.
2018. Proceedings of the 13th International Symposium on Applied Reconfigurable Computing, ARC 2018, Santorini, Greece, 2nd - 4th May 2018
The ARAMiS Project Initiative : Multicore Systems in Safety- and Mixed-Critical Applications
Becker, J.; Bapp, F.
2018. Proceedings of the 14th International Symposium on Applied Reconfigurable Computing, ARC 2018, Santorini, Greece, 2nd - 4th May 2018
Forschungsberichte/Preprints
Towards Fail-Operational Systems on Controller Level Using Heterogeneous Multicore SoC Architectures and Hardware Support
Bapp, F. K.; Dörr, T.; Sandmann, T.; Schade, F.; Becker, J.
2018. SAE International. doi:10.4271/2018-01-1072
Vorträge
In-NoC circuits for low-latency cache coherence in distributed shared-memory architectures
Masing, L.; Srivatsa, A.; Kreß, F.; Anantharajaiah, N.; Herkersdorf, A.; Becker, J.
2018. 12th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2018), Hanoi, Vietnam, 12.–14. September 2018
2017
Zeitschriftenaufsätze
A precision device needs precise simulation: Software description of the CBM Silicon Tracking System
CBM Collaboration; Malygina, H.; Friese, V.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2017. Journal of Physics: Conference Series, 898, Art.-Nr.: 042022. doi:10.1088/1742-6596/898/4/042022
The high-rate data challenge: computing for the CBM experiment
CBM Collaboration; Friese, V.; Bähr, S.; Balzer, M.; Becker, J.; Blank, T.; Caselle, M.; Sidorenko, V.; Trifonova, E.; Unger, K. L.; Weber, M.
2017. Journal of Physics: Conference Series, 898, Art.-Nr. 112003. doi:10.1088/1742-6596/898/11/112003
A Generic Reconfigurable Mixed Time and Frequency Domain QAM Transmitter with Forward Error Correction
Figuli, S.; Figuli, P.; Sonnino, A.; Becker, J.
2017. International Journal of Advances in Telecommunications, Electrotechnics, Signals and Systems, 6 (2), 80–88
Foreword to the Special Section on Reconfigurable Computing
Derrien, S.; Atasu, K.; Cardoso, J. M. P.; Becker, J.
2017. Journal of signal processing systems, 88 (2), 103–105. doi:10.1007/s11265-017-1237-7
A Timing Synchronizer System for Beam Test Setups Requiring Galvanic Isolation
Meder, L. D.; Emschermann, D.; Frühauf, J.; Müller, W. F. J.; Becker, J.
2017. IEEE transactions on nuclear science, 64 (7), 1975–1982. doi:10.1109/TNS.2017.2713524
A neural network on FPGAs for the z-vertex track trigger in Belle II
Bähr, S.; Skambraks, S.; Neuhaus, S.; Kiesling, C.; Becker, J.
2017. Journal of Instrumentation, 12, Art. Nr.: C03065. doi:10.1088/1748-0221/12/03/C03065
A versatile small form factor twisted-pair TFC FMC for MTCA AMCs
Meder, L.; Lebedev, J.; Becker, J.
2017. Journal of Instrumentation, 12 (3), Art. Nr.: C03074. doi:10.1088/1748-0221/12/03/C03074
Challenges in QCD matter physics –The scientific programme of the Compressed Baryonic Matter experiment at FAIR
Ablyazimov, T.; Abuhoza, A.; Adak, R. P.; Adamczyk, M.; Agarwal, K.; Aggarwal, M. M.; Ahammed, Z.; Ahmad, F.; Ahmad, N.; Ahmad, S.; Akindinov, A.; Akishin, P.; Akishina, E.; Akishina, T.; Akishina, V.; Akram, A.; Al-Turany, M.; Alekseev, I.; Becker, K.-H.; Becker, J.; u. a.
2017. The European physical journal / A, 53 (3), 60. doi:10.1140/epja/i2017-12248-y
The promised future of multi-core processors in avionics systems
Sander, O.; Bapp, F.; Dieudonne, L.; Sandmann, T.; Becker, J.
2017. CEAS Aeronautical Journal, 8 (1), 143–155. doi:10.1007/s13272-016-0228-x
Proceedingsbeiträge
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration
Harbaum, T.; Schade, C.; Damschen, M.; Tradowsky, C.; Bauer, L.; Henkel, J.; Becker, J.
2017. 2017 30th IEEE International System-on-Chip Conference (SOCC), Munich, 5–8 September 2017, 153–158, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2017.8226027
Opening remarks
Becker, J.
2017. 2017 30th IEEE International System-on-Chip Conference (SOCC), Munich, Germany, 5–8 September 2017, 1 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2017.8225988
A Non-Invasive Cyberrisk in Cooperative Driving
Bapp, F.; Becker, J.; Beyerer, J.; Doll, J.; Filsinger, M.; Frese, C.; Hubschneider, C.; Lauber, A.; Müller-Quade, J.; Pauli, M.; Roschani, M.; Salscheider, O.; Rosenhahn, B.; Ruf, M.; Stiller, C.; Willersinn, D.; Ziehn, J. R.
2017. TÜV-Tagung Fahrerassistenz, 2017, München, 8 S
A Reconfigurable High-speed Spiral FIR Filter Architecture
Figuli, S. P. D.; Figuli, P.; Becker, J.
2017. Proceedings of the 40th International Conference on Telecommunications and Signal Processing, TSP 2017, Barcelona, Spain, 5th - 7th July 2017, 532–537, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/TSP.2017.8076044
Increasing Energy Efficiency Through Semi-Automatic Parallelization of Applications for Embedded Computing Devices in the IoT Domain
Oey, O.; Rueckauer, M.; Stripf, T.; Becker, J.
2017. Embedded World Conference 2017, 14. bis 16. März 2017, Nürnberg
WCET-aware parallelization of model-based applications for multi-cores : The ARGO approach
Derrien, S.; Puaut, I.; Alefragis, P.; Bednara, M.; Bucher, H.; David, C.; Debray, Y.; Durak, U.; Fassi, I.; Ferdinand, C.; Hardy, D.; Kritikakou, A.; Rauwerda, G.; Reder, S.; Sicks, M.; Stripf, T.; Sunesen, K.; Ter Braak, T.; Voros, N.; Becker, J.
2017. Proceedings of the 20th Design, Automation and Test in Europe, Lausanne, Switzerland, 27-31 March 2017, 286–289, Institute of Electrical and Electronics Engineers (IEEE). doi:10.23919/DATE.2017.7927000
An Integrated Approach Enabling Cross-Domain Simulation of Model-Based E/E-Architectures
Bucher, H.; Reichmann, C.; Becker, J.
2017. SAE World Congress Experience, WCX 2017, Detroit, United States, 4th - 6th April 2017, 14 S., SAE International. doi:10.4271/2017-01-0006
Parameter Sensitivity in Virtual FPGA Architectures
Figuli, P.; Ding, W.; Figuli, S.; Siozios, K.; Soudris, D.; Becker, J.
2017. 13th International Symposium on Applied Reconfigurable Computing, ARC 2017; Delft; Netherlands; 3 April 2017 through 7 April 2017. Ed. : S. Wong, 141–153, Springer International Publishing. doi:10.1007/978-3-319-56258-2_13
Energy efficient scientific computing on FPGAs using OpenCL
Weller, D.; Oboril, F.; Lukarski, D.; Becker, J.; Tahoori, M.
2017. FPGA ’17 Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February 22 - 24, 2017, 247–256, Association for Computing Machinery (ACM). doi:10.1145/3020078.3021730
Dissertationen
Automated Hardware Prototyping for 3D Network on Chips. Dissertation
Friederich, S.
2017. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000078077
Eine adaptive Architekturbeschreibung für eingebettete Multicoresysteme. Dissertation
Bruckschlögl, T.
2017. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000073629
Timing Synchronization and Fast-Control for FPGA-based large-scale Readout and Processing Systems. Dissertation
Meder, L. D.
2017. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000071051
2016
Zeitschriftenaufsätze
Providing fault tolerance through invasive computing
Lari, V.; Weichslgartner, A.; Tanase, A.; Witterauf, M.; Khosravi, F.; Teich, J.; Heißwolf, J.; Friederich, S.; Becker, J.
2016. Information technology, 58 (6), 309–328. doi:10.1515/itit-2016-0022
A signal distribution board for the timing and fast control master of the CBM experiment
Meder, L.; Dreschmann, M.; Sander, O.; Becker, J.
2016. Journal of Instrumentation, 11 (2), Art. Nr.: C02001. doi:10.1088/1748-0221/11/02/C02001
A V2X Message Evaluation Methodology and Cross-Domain Modelling of Safety Applications in V2X-enabled E/E-Architectures
Bucher, H.; Buciuman, M.-F.; Klimm, A.; Sander, O.; Becker, J.
2016. EAI Endorsed Transactions on Security and Safety, 16 (8), Art.Nr. e1. doi:10.4108/eai.24-8-2015.2261038
Efficient task spawning for shared memory and message passing in many-core architectures
Zaib, A.; Wild, T.; Herkersdorf, A.; Heisswolf, J.; Becker, J.; Weichslgartner, A.; Teich, J.
2016. Journal of systems architecture, 77, 72–82. doi:10.1016/j.sysarc.2017.03.004
A framework for porting the NeuroBayes machine learning algorithm to FPGAs
Baehr, S.; Sander, O.; Heck, M.; Feindt, M.; Becker, J.
2016. Journal of Instrumentation, 11 (1), Art. Nr.: C01058. doi:10.1088/1748-0221/11/01/C01058
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography
Birk, M.; Kretzek, E.; Figuli, P.; Weber, M.; Becker, J.; Ruiter, N. V.
2016. IEEE transactions on parallel and distributed systems, 27 (2), 455–467. doi:10.1109/TPDS.2015.2405508
An introductory microcontroller programming laboratory course for first-year students
Nürnberg, T.; Beuth, T.; Becker, J.; Puente León, F.
2016. International journal of electrical engineering education, 53 (2), 99–113. doi:10.1177/0020720915611439
Cloud-based design and virtual prototypin environment for embedded systems
Werner, S.; Lauber, A.; Koedam, M.; Becker, J.; Sax, E.; Goossens, K.
2016. International journal of online engineering, 12 (9), 52–60. doi:10.3991/ijoe.v12i09.6142
Development of a Latency Optimized Communication Device for WAVE and SAE Based V2X-Applications
Pistorius, F.; Lauber, A.; Pfau, J.; Klimm, A.; Becker, J.
2016. SAE technical papers, 2016-April, 1–11. doi:10.4271/2016-01-0150
Proceedingsbeiträge
SoC design methods and algorithms II
Becker, J.
2016. 2016 29th IEEE International System-on-Chip Conference (SOCC), Seattle, WA, USA, 6–9 September 2016, 1 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2016.7905493
Application specific SoC designs
Becker, J.
2016. 2016 29th IEEE International System-on-Chip Conference (SOCC), Seattle, WA, USA, 6–9 September 2016, 1 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2016.7905438
Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication
Pande, P.; Becker, J.
2016. 2016 29th IEEE International System-on-Chip Conference (SOCC), Seattle, WA, USA, 6–9 September 2016, 1–2, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2016.7905411
Tutorial 2A: 3D integration - challenges and advantages
Chrzanowska-Jeske, M.; Becker, J.
2016. 2016 29th IEEE International System-on-Chip Conference (SOCC), Seattle, WA, USA, 6–9 September 2016, 1–3, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SOCC.2016.7905409
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing
Figuli, S. P. D.; Sonnino, A.; Figuli, P.; Becker, J.
2016. 2016 39th International Conference on Telecommunications and Signal Processing (TSP), Vienna, Austria, 27–29 June 2016. Ed.: N. Herencsar, 453–457, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/TSP.2016.7760919
A Novel NoC-Architecture for Fault Tolerance and Power Saving
Heisswolf, J.; Friederich, S.; Masing, L.; Weichslgartner, A.; Zaib, A.; Stein, C.; Duden, M.; Teich, J.; Herkersdorf, A.; Becker, J.
2016. Proceedings of the second International Workshop on Multi-Objective Many-Core Design (MOMAC) in conjunction with International Conference on Architecture of Computing Systems (ARCS). 5. April 2016, Nürnberg, Institute of Electrical and Electronics Engineers (IEEE)
A Novel ADL-based Approach to Design Adaptive Application-Specific Processors
Tradowsky, C.; Harbaum, T.; Masing, L.; Becker, J.
2016. Best of ISVLSI 2016, Pittsburgh, Pennsylvania, U.S.A., July 11-13, 2016, Springer
Adaptive Bandwidth Router for 3D Network-on-Chips
Friederich, S.; Lehmann, N.; Becker, J.
2016. 12th International Symposium on Applied Reconfigurable Computing, ARC 2016; Mangaratiba; Brazil; 22 March 2016 through 24 March 2016. Ed.: V. Bonato, 352–360, Springer International Publishing. doi:10.1007/978-3-319-30481-6_30
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems
Tradowsky, C.; Cordero, E.; Orsinger, C.; Vesper, M.; Becker, J.
2016. 12th International Symposium on Applied Reconfigurable Computing, ARC 2016; Mangaratiba; Brazil; 22 March 2016 through 24 March 2016. Ed.: V. Bonato, 343–351, Springer International Publishing. doi:10.1007/978-3-319-30481-6_29
Adaptive Cache Structures
Tradowsky, C.; Cordero, E.; Orsinger, C.; Vesper, M.; Becker, J.
2016. 29th International Conference on Architecture of Computing Systems, ARCS 2016; Nuremberg; Germany; 4 April 2016 through 7 April 2016. Ed.: F. Hannig, 87–99, Springer International Publishing. doi:10.1007/978-3-319-30695-7_7
Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures
Bapp, F. K.; Sander, O.; Sandmann, T.; Stoll, H.; Becker, J.
2016. 12th International Symposium on Applied Reconfigurable Computing, ARC 2016; Mangaratiba; Brazil; 22 March 2016 through 24 March 2016. Ed.: V. Bonato, 273–286, Springer International Publishing. doi:10.1007/978-3-319-30481-6_22
Power Management Controller for Online Power Saving in Network-on-Chips
Friederich, S.; Neber, M.; Becker, J.
2016. 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Lyon, France, 21–23 September 2016, 109–116, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/MCSoC.2016.22
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
Sotiriou-Xanthopoulos, E.; Masing, L.; Siozios, K.; Economakos, G.; Soudris, D.; Becker, J.
2016. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XVI), Samos, GR, July 17-21, 2016. Proceedings. Ed.: W. Najjar, 372–377, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SAMOS.2016.7818375
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment
Harbaum, T.; Seboui, M.; Balzer, M.; Becker, J.; Weber, M.
2016. 24th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2016; Washington; United States; 1 May 2016 through 3 May 2016, 184–191, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FCCM.2016.52
A timing synchronizer system for beam test setups requiring galvanic isolation
Meder, L.; Emschermann, D.; Frühauf, J.; Muller, W. F. J.; Becker, J.
2016. IEEE-NPSS Real Time Conference (RT), Padova; Italy; 6 - 10 June 2016, 7543119, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/RTC.2016.7543119
Cloud-based remote virtual prototyping platform for embedded control applications: Cloud-based infrastructure for large-scale embedded hardware-related programming laboratories
Werner, S.; Lauber, A.; Becker, J.; Sax, E.
2016. Proceedings of 2016 13th International Conference on Remote Engineering and Virtual Instrumentation, REV 2016, Madrid; Spain; 24 February 2016 through 26 February 2016, Art.Nr.: 7444459, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/REV.2016.7444459
Dissertationen
Methoden zur applikationsspezifischen Effizienzsteigerung adaptiver Prozessorplattformen. Dissertation
Tradowsky, C.
2016. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000067258
Realisierung einer adaptiven parallelen Hardwarearchitektur für hochperformante OFDMA. Dissertation
Dreschmann, M.
2016. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000066061
2015
Zeitschriftenaufsätze
Parallelization of genetic algorithms for sorting permutations by reversals over biological data
Soncco-Álvarez, J. L.; Almeida, G. M.; Becker, J.; Ayala-Rincón, M.
2015. International journal of hybrid intelligent systems, 12 (1), 53–64. doi:10.3233/HIS-140205
The Road to “ITIV Labs” – an Integrated Concept for Project-Oriented Systems Engineering Education
Beuth, T.; Gaedeke, T.; Tradowsky, C.; Becker, J.; Klimm, A.; Sander, O.
2015. International Journal of Information and Education Technology, 5 (4), 250–254. doi:10.7763/IJIET.2015.V5.511
Online-Analysis of Hits in the Belle-II Pixeldetector for Separation of Slow Pions from Background
Baehr, S.; Sander, O.; Heck, M.; Pulvermacher, C.; Feindt, M.; Becker, J.
2015. Journal of physics / Conference Series, 664 (9), Art.Nr. 092001. doi:10.1088/1742-6596/664/9/092001
Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures
Reder, S.; Roth, C.; Bucher, H.; Sander, O.; Becker, J.
2015. Microprocessors and microsystems, 39 (8), 1063–1075. doi:10.1016/j.micpro.2015.06.001
Ultra-Dense, Single-Wavelength DFT-Spread OFDMA PON with Laserless 1.2 Gb/s ONU Ready for Silicon Photonics Integration
Schindler, P. C.; Agmon, A.; Wolf, S.; Bonk, R.; Meder, L.; Meltsin, M.; Ludwig, A.; Schmogrow, R.; Dreschmann, M.; Meyer, J.; Becker, J.; Nazarathy, M.; Ben-Ezra, S.; Pfeiffer, T.; Freude, W.; Leuthold, J.; Koos, C.
2015. Journal of Lightwave Technology, 33 (8), 1650–1659. doi:10.1109/JLT.2014.2386215
Proceedingsbeiträge
Network Interface with Task Spawning Support for NoC-Based DSM Architectures
Zaib, A.; Heißwolf, J.; Weichslgartner, A.; Wild, T.; Teich, J.; Becker, J.; Herkersdorf, A.
2015. 28th International Conference on Architecture of Computing Systems, ARCS 2015; Porto; Portugal; 24 March 2015 through 27 March 2015. Ed.: L. M. Pinho, 186–198, Springer International Publishing. doi:10.1007/978-3-319-16086-3_15
Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures
Weichslgartner, A.; Heisswolf, J.; Zaib, A.; Wild, T.; Herkersdorf, A.; Becker, J.; Teich, J.
2015. ARCS 2015 : workshop proceedings / 28th International Conference on Architecture of Computing Systems, March 24 - 27, 2015, Porto, Portugal, School of Engineering of the Polytechnic of Porto (ISEP), 1–4, VDE Verlag
A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers
Dreschmann, M.; Heisswolf, J.; Geiger, M.; Haußecker, M.; Becker, J.
2015. 28th Symposium on Integrated Circuits and Systems Design, SBCCI 2015; Salvador, Bahia; Brazil; 31 August 2015 through 4 September 2015, Art. Nr.: 5, Association for Computing Machinery (ACM). doi:10.1145/2800986.2800993
RAW Introduction and Committees
Becker, J.; Eguro, K.; Gohringer, D.; Luk, W.; Santambrogio, M. D.; Vaidyanathan, R.; Wilton, S.
2015. 29th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015; Hyderabad; India; 25 May 2015 through 29 May 2015, 68–69, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IPDPSW.2015.157
Multiplier-free carrier-phase recovery for real-time receivers using processing in polar coordinates
Baeuerle, B.; Josten, A.; Abrecht, F.; Dornbierer, E.; Boesser, J.; Dreschmann, M.; Becker, J.; Leuthold, J.; Hillerkuss, D.
2015. Proceedings of the 2015 Optical Fiber Communications Conference and Exhibition, OFC 2015, Los Angeles, California, USA, 22nd - 26th March 2015, Art.Nr. 7121905, Institute of Electrical and Electronics Engineers (IEEE)
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip
Werner, S.; Stiehle, B.; Becker, J.
2015. Conference on Design and Architectures for Signal and Image Processing, DASIP 2015; Cracow; Poland; 23 September 2015 through 25 September 2015. Ed.: S. Cerisier, Art. Nr.: 7367260, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DASIP.2015.7367260
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
Figuli, P.; Tradowsky, C.; Martinez, J.; Sidiropoulos, H.; Siozios, K.; Stenschke, H.; Soudris, D.; Becker, J.
2015. 11th International Symposium on Applied Reconfigurable Computing, ARC 2015; Bochum; Germany; 13 April 2015 through 17 April 2015. Ed.: K. Sano, 311–320, Springer International Publishing. doi:10.1007/978-3-319-16214-0_26
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
Siozios, K.; Figuli, P.; Sidiropoulos, H.; Tradowsky, C.; Diamantopoulos, D.; Maragos, K.; Delicia, S. P.; Soudris, D.; Becker, J.
2015. 11th International Symposium on Applied Reconfigurable Computing, ARC 2015; Bochum; Germany; 13 April 2015 through 17 April 2015. Ed.: K. Sano, 103–114, Springer International Publishing. doi:10.1007/978-3-319-16214-0_9
Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms
Werner, S.; Masing, L.; Lesniak, F.; Becker, J.
2015. 2015 25th International Conference on Field Programmable Logic and Applications (FPL), London, United Kingdom, 2–4 September 2015, Art.Nr. 7294020, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPL.2015.7294020
Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms
Masing, L.; Werner, S.; Becker, J.
2015. 2015 10th IEEE International Symposium on Industrial Embedded Systems (SIES), Siegen, Germany, 8–10 June 2015, 152–155, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SIES.2015.7185053
Fault-tolerant Communication in Invasive Networks on Chip
Heisswolf, J.; Weichslgartner, A.; Zaib, A.; Friederich, S.; Masing, L.; Duden, M.; Klöpfer, R.; Teich, J.; Wild, T.; Herkersdorf, A.; Becker, J.
2015. Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, June 15-18, 2015, Montreal, Canada, Art.Nr. 7231156. doi:10.1109/AHS.2015.7231156
A V2X Message Evaluation Methodology and Cross-Domain Modelling of Safety Applications in V2X-enabled E/E-Architectures
Bucher, H.; Buciuman, M.-F.; Klimm, A.; Sander, O.; Becker, J.
2015. Proceedings of the 8th International Conference on Simulation Tools and Techniques : 24-26 August 2015, Athens, Greece ; SIMUTools 2015. Ed.: Gary S. H. Tan, 71–78, ICST
On-demand reconfiguration for coprocessors in mixed criticality multicore systems
Viet Vu, D.; Sander, O.; Sandmann, T.; Heidelberger, J.; Baehr, S.; Becker, J.
2015. 2015 International Conference on High Performance Computing & Simulation (HPCS), Amsterdam, Netherlands, 20–24 July 2015. Ed.: Waleed W. Smari, 569–576, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/HPCSim.2015.7237094
Two Architecture Approaches for MILS Systems in Mobility Domains (Automobile, Railway and Avionik)
Adam, D.; Tverdyshev, S.; Rolfes, C.; Sandmann, T.; Baehr, S.; Sander, O.; Becker, J.; Baumgarten, U.
2015. International Workshop on MILS: Architecture and Assurance for Secure Systems (MILS 2015), 20.01.2015, Amsterdam
Embedded Virtualization Approaches for Ensuring Safety and Security within E/E Automotive Systems
Reinhardt, D.; Adam, D.; Lubbers, E.; Amarnath, R.; Schneider, R.; Gansel, S.; Schnitzer, S.; Herber, C.; Sandmann, T.; Michel, H. U.; Kaule, D.; Olkun, D.; Rehm, M.; Harnisch, J.; Richter, A.; Baehr, S.; Sander, O.; Becker, J.; Baumgarten, U.; Theiling, H.
2015. Embedded World Conference, Nürnberg, February 24 - 26, 2015
On-Demand Reconfiguration for Coprocessors in Mixed Criticality Multicore Systems
Viet Vu, D.; Sander, O.; Sandmann, T.; Heidelberger, J.; Baehr, S.; Becker, J.
2015. 7th International Workshop on Dependable Many-Core Computing (DMCC 2015), Amsterdam, July 20 – July 24, 2015
A distributed simulation platform using HLA for complex embedded systems design
Brito, A. V.; Bucher, H.; Oliveira, H.; Costa, L. F. S.; Sander, O.; Melcher, E. U. K.; Becker, J.
2015. 19th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, DS-RT 2015, Chengdu, Sichuan, China, October 14-16, 2015. Proceedings, 195–202, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DS-RT.2015.16
Power estimation of an ECDSA core applied in V2X scenarios using heterogeneous distributed simulation
Bucher, H.; Klimm, A.; Sander, O.; Becker, J.
2015. 19th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, DS-RT 2015, Chengdu, Sichuan, China, October 14-16, 2015. Proceedings, 187–194, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DS-RT.2015.35
Designing applications for heterogeneous many-core architectures with the FlexTiles Platform
Janßen, B.; Schwiegelshohn, F.; Koedam, M.; Duhem, F.; Masing, L.; Werner, S.; Huriaux, C.; Courtay, A.; Wheatley, E.; Goossens, K.; Lemonnier, F.; Millet, P. T.; Becker, J.; Sentieys, O.; Hübner, M.
2015. 15th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2015, Samos, Greece, 254–261, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SAMOS.2015.7363683
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models
Sotiriou-Xanthopoulos, E.; Delicia, G. S. P.; Figuli, P.; Siozios, K.; Economakos, G.; Becker, J.
2015. 2015 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2015, Greece, 70–77, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SAMOS.2015.7363661
Parametric design space exploration for optimizing QAM based high-speed communication
Delicia George Ford, S. P.; Figuli, P.; Becker, J.
2015. IEEE/CIC ICCC 2015 Symposium on Communication and Control Theory : IEEE/CIC International Conference on Communications in China, ICCC 2015; Shenzhen; China; 2 November 2015 through 5 November 2015, Art.Nr.: 7448662, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICCChina.2015.7448662
Design of an embedded UWB hardware platform for navigation in GPS denied environments
Hartmann, F.; Pistorius, F.; Lauber, A.; Hildenbrand, K.; Becker, J.; Stork, W.
2015. 2015 IEEE Symposium on Communications and Vehicular Technology in the Benelux (SCVT) : 24 November 2015, Luxembourg, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SCVT.2015.7374232
Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUs
Meder, L.; Schindler, P. C.; Agmon, A.; Meltsin, M.; Bonk, R.; Meyer, J.; Dreschmann, M.; Tolmachev, A.; Hilgendorf, R.; Nazarathy, M.; Ben-Ezra, S.; Pfeiffer, T.; Freude, W.; Leuthold, J.; Koos, C.; Becker, J.
2015. 2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014; Madrid; Spain; 8 October 2014 through 10 October 2014, Art. Nr.: 7115601, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DASIP.2014.7115601
Forschungsberichte/Preprints
Adapting Commercial Off-The-Shelf Multicore Processors for Safety-Related Automotive Systems Using Online Monitoring
Bapp, F. K.; Sander, O.; Sandmann, T.; Vu Duy, V.; Baehr, S.; Becker, J.
2015. SAE International. doi:10.4271/2015-01-0280
2014
Bücher
Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors
Azambuja, J. R.; Kastensmidt, F.; Becker, J.
2014. Springer International Publishing. doi:10.1007/978-3-319-06340-9
Zeitschriftenaufsätze
GPU-based iterative transmission reconstruction in 3D ultrasound computer tomography
Birk, M.; Dapp, R.; Ruiter, N. V.; Becker, J.
2014. Journal of Parallel and Distributed Computing, 74 (1), 1730–1743. doi:10.1016/j.jpdc.2013.09.007
Demonstration of an SOA-assisted open metro-access infrastructure for heterogeneous services
Schmuck, H.; Bonk, R.; Poehlmann, W.; Haslach, C.; Kuebart, W.; Karnick, D.; Meyer, J.; Fritzsche, D.; Weis, E.; Becker, J.; Freude, W.; Pfeiffer, T.
2014. Optics express, 22 (1), 737–748. doi:10.1364/OE.22.000737
Real-time Nyquist signaling with dynamic precision and flexible non-integer oversampling
Schmogrow, R.; Meyer, M.; Schindler, P. C.; Nebendahl, B.; Dreschmann, M.; Meyer, J.; Josten, A.; Hillerkuss, D.; Ben-Ezra, S.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
2014. Optics express, 22 (1), 193–209. doi:10.1364/OE.22.000193
A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography
Birk, M.; Zapf, M.; Balzer, M.; Ruiter, N.; Becker, J.
2014. Journal of Real-Time Image Processing, 9 (1), 159–170. doi:10.1007/s11554-012-0267-4
Proceedingsbeiträge
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure
Heisswolf, J.; Zaib, A.; Weichslgartner, A.; Karle, M.; Singh, M.; Wild, T.; Teich, J.; Herkersdorf, A.; Becker, J.
2014. ARCS 2014 : workshop proceedings / 27th International Conference on Architecture of Computing Systems, February 25 – 28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering. Ed.: W. Stechele, 1–8, VDE Verlag
Adaptive Algorithm and Tool Flow for Accelerating SystemC on Many-Core Architectures
Roth, C.; Reder, S.; Bucher, H.; Sander, O.; Becker, J.
2014. 17th Euromicro Conference on Digital System Design, DSD 2014; Verona; Italy; 27 August 2014 through 29 August 2014, 137–145, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD.2014.62
SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor
Tradowsky, C.; Gadeke, T.; Bruckschlogl, T.; Stork, W.; Muller-Glaser, K.-D.; Becker, J.
2014. 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2014; Turin; Italy; 12 February 2014 through 14 February 2014, 478–481, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/PDP.2014.118
A Hierarchical Architecture Description for Flexible Multicore System Simulation
Bruckschloegl, T.; Oey, O.; Rueckauer, M.; Stripf, T.; Becker, J.
2014. 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPA), 190–196, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISPA.2014.33
A Simulation Tool Chain for Investigating Future V2X-based Automotive E/E Architectures
Roth, C.; Bucher, H.; Brito, A.; Sander, O.; Becker, J.
2014. Proceedings of the 7th European Congress on Embedded Real Time Software and Systems (ERTS²), 4 - 7 February 2014, Toulouse, France
Architectural Measures Against Radiation Effects in Multicore SoC for Safety Critical Applications
Sander, O.; Bapp, F.; Sandmann, T.; Viet Vu, D.; Baehr, S.; Becker, J.
2014. IEEE 57th Midwest Symposium on Circuits and Systems (MWSCAS 14), 3-6 Aug. 2014, College Station, TX, USA. doi:10.1109/MWSCAS.2014.6908502
Hardware virtualization support for shared resources in mixed-criticality multicore systems
Sander, O.; Sandmann, T.; Viet Vu, D.; Baehr, S.; Bapp, F.; Becker, J.; Michel, H. U.; Kaule, D.; Adam, D.; Lubbers, E.; Hairbucher, J.; Richter, A.; Herber, C.; Herkersdorf, A.
2014. 17th Design, Automation and Test in Europe, DATE 2014; Dresden; Germany; 24 - 28 March 2014, Art.Nr. 6800282. doi:10.7873/date.2014.081
Virtualization Support for FPGA-based Coprocessors Connected via PCI Express to an Intel Multicore Platform
Viet Vu, D.; Sandmann, T.; Baehr, S.; Sander, O.; Becker, J.
2014. IEEE 28th International Parallel & Distributed Processing Symposium Workshops : proceedings : IPDPSW 2014 : 19-23 May 2014, Phoenix, Arizona, 305–310, IEEE Computer Society. doi:10.1109/IPDPSW.2014.42
Enabling Partial Reconfiguration for Coprocessors in Mixed Criticality Multicore Systems Using PCI Express Single-Root I/O Virtualization
Vu, D. V.; Sander, O.; Sandmann, T.; Baehr, S.; Heidelberger, J.; Becker, J.
2014. 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig 2014), Cancun, Mexico, December 8 - 10, 2014. Ed.: M. Huebner, 38–75, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ReConFig.2014.7032516
A Flexible Interface Architecture for Reconfigurable Coprocessors in Embedded Multicore Systems using PCIe Single-Root I/O Virtualization
Sander, O.; Sandmann, T.; Baehr, S.; Viet Vu, D.; Lubbers, E.; Becker, J.
2014. The 2014 International Conference on Field-Programmable Technology (ICFPT 2014), Shanghai, China, December 10 - 12, 2014. Ed.: J. Chen, 223–226, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPT.2014.7082780
Towards Dynamic Cache and Bandwidth Invasion
Tradowsky, C.; Schreiber, M.; Vesper, M.; Domladovec, I.; Braun, M.; Bungartz, H.-J.; Becker, J.
2014. Reconfigurable Computing: Architectures, Tools, and Applications : 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings. Ed.: D.Göhringer, 97–107, Springer. doi:10.1007/978-3-319-05960-0_9
Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems
Becker, J.; Bruckschloegl, T.; Oey, O.; Stripf, T.; Goulas, G.; Raptis, N.; Valouxis, C.; Alefragis, P.; Voros, N. S.; Gogos, C.
2014. Reconfigurable Computing: Architectures, Tools, and Applications : 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings. Ed.: D.Göhringer, 330–336, Springer. doi:10.1007/978-3-319-05960-0_37
Ultra-dense, single-wavelength DFT-spread OFDM PON with laserless 1 Gb/s ONU at only 300 MBd per spectral group
Schindler, P. C.; Agmon, A.; Wolf, S.; Bonk, R.; Meder, L.; Meltsin, M.; Ludwig, A.; Becker, J.; Nazarathy, M.; Ben-Ezra, S.; Pfeiffer, T.; Freude, W.; Leuthold, J.; Koos, C.
2014. 2014 European Conference on Optical Communication, ECOC 2014; Cannes; France; 21 September 2014 - 25 September 2014, Art. Nr.: 6964097, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ECOC.2014.6964097
CAP: Communication aware programming
Heisswolf, J.; Zaib, A.; Zwinkau, A.; Kobbe, S.; Weichslgartner, A.; Teich, J.; Henkel, J.; Snelting, G.; Herkersdorf, A.; Becker, J.
2014. 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14), San Francisco, California/USA, June 1-5, 2014, 1–6, Association for Computing Machinery (ACM). doi:10.1145/2593069.2593103
Dissertationen
Methodischer Beitrag zum neuen Einsatz von Techniken der formalen Verifikation bei seriellen Busprotokollen im automobilen Umfeld. Dissertation
Becker, J. E.
2014. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000050508
Parallele und kooperative Simulation für eingebettete Multiprozessorsysteme. Dissertation
Roth, C.
2014. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000046592
A Scalable and Adaptive Network on Chip for Many-Core Architectures. Dissertation
Heißwolf, J.
2014. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000045305
HW/SW Co-Design Framework für Hochgeschwindigkeits-OFDM Signalverarbeitung. Dissertation
Meyer, J. H.
2014. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000045040
2013
Buchaufsätze
Embedded Systems Start-Up Under Timing Constraints on Modern FPGAs
Meyer, J.; Noguera, J.; Hübner, M.; Stewart, R.; Becker, J.
2013. Embedded Systems Design with FPGAs. Ed.: P. Athanas, 149–172, Springer-Verlag. doi:10.1007/978-1-4614-1362-2_7
Zeitschriftenaufsätze
HETA: Hybrid error-detection technique using assertions
Azambuja, J. R.; Altieri, M.; Becker, J.; Kastensmidt, F. L.
2013. IEEE Transactions on Nuclear Science, 60 (4), 2805–2812. doi:10.1109/TNS.2013.2246798
Compiling Scilab to high performance embedded multicore systems
Stripf, T.; Oey, O.; Bruckschloegl, T.; Becker, J.; Rauwerda, G.; Sunesen, K.; Goulas, G.; Alefragis, P.; Voros, N. S.; Derrien, S.; Sentieys, O.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Kritharidis, D.; Mitas, N.; Perschke, T.
2013. Microprocessors and Microsystems, 37 (8 Part C), 1033–1049. doi:10.1016/j.micpro.2013.07.004
Colorless FDMA-PON with flexible bandwidth allocation and colorless, low-speed ONUs
Schindler, P. C.; Schmogrow, R.; Dreschmann, M.; Meyer, J.; Tomkos, I.; Prat, J.; Krimmel, H.-G.; Pfeiffer, T.; Kourtessis, P.; Ludwig, A.; Karnick, D.; Hillerkuss, D.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
2013. IEEE/OSA Journal of Optical Communications and Networking, 5 (10), A204-A212. doi:10.1364/JOCN.5.00A204
Novel Techniques for Smart Adaptive Multiprocessor SoCs
Ost, L.; Garibotti, R.; Sassatelli, G.; Marchesan Almeida, G.; Busseuil, R.; Butko, A.; Robert, M.; Becker, J.
2013. IEEE Transactions on Computers, PP (99), 1/1–1. doi:10.1109/TC.2013.57
Providing multiple hard latency and throughput guarantees for packet switching networks on chip
Heisswolf, J.; König, R.; Kupper, M.; Becker, J.
2013. Computers & electrical engineering, 39 (8), 2603–2622. doi:10.1016/j.compeleceng.2013.06.005
Reliable and adaptive network-on-chip architectures for cyber physical systems
Göhringer, D.; Meder, L.; Oey, O.; Becker, J.
2013. ACM Transactions on Embedded Computing Systems, 12 (1), 51/1–21. doi:10.1145/2435227.2435247
Virtual networks - distributed communication resource management
Heisswolf, J.; Zaib, A.; Weichslgartner, A.; König, R.; Wild, T.; Teich, J.; Herkersdorf, A.; Becker, J.
2013. ACM Transactions on Reconfigurable Technology and Systems, 6 (2), 8/1–14. doi:10.1145/2492186
JITPR: A framework for supporting fast application’s implementation onto FPGAs
Sidiropoulos, H.; Siozios, H.; Figuli, P.; Soudris, D.; Hübner, M.; Becker, J.
2013. ACM Transactions on Reconfigurable Technology and Systems, 6 (2), 7/1–12. doi:10.1145/2492185
Proceedingsbeiträge
Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms
Uhl, A.; Becker, J.
2013. Proceedings of the 16th Euromicro Conference on Digital System Design, DSD 2013, Los Alamitos, California, USA, 4th - 6th September 2013, 129–135, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD.2013.22
An FPGA-based multi-core approach for pipelining computing stages
Azarian, A.; Cardoso, J. M. P.; Werner, S.; Becker, J.
2013. 28th Annual ACM Symposium on Applied Computing, SAC 2013; Coimbra; Portugal; 18 March 2013 through 22 March 2013, 1533–1540, Association for Computing Machinery (ACM). doi:10.1145/2480362.2480647
Hardware based Coprocessor Scheduling for Safety Critical Applications in Automotive and Avionics
Sander, O.; Sandmann, T.; Viet Vu, D.; Bapp, F.; Becker, J.
2013. International Conference on Computing, Networking and Communications (ICNC 2014), Honolulu, Hawaii, USA, February 3-6, 2014
Development and evaluation of distributed simulation of embedded systems using ptolemy and HLA
Brito, A. V.; Negreiros, A. V.; Roth, C.; Sander, O.; Becker, J.
2013. Proceedings - 17th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications - DS-RT 2013, 30 October - 1 November 2013, Delft, Netherlands, 189–196, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DS-RT.2013.28
Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation
Heisswolf, J.; Singh, M.; Kupper, M.; König, R.; Becker, J.
2013. 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, Cancun, Mexico December 9-11, 2013. Ed.: R. Cumplido, 1–8, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ReConFig.2013.6732328
A Platform-Independant Runtime Methodology for Mapping Multiple Applications onto FPGAs through Resource Virtualization
Sidiropoulos, H.; Figuli, P.; Siozos, K.; Soudris, D.; Becker, J.
2013. 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013, Porto, Portugal, Sept. 2 - 4, 2013, proceedings. Ed.: J. M. P. Cardoso, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPL.2013.6645564
Addiguration: Exploring configuration behavior of Spartan-3 devices
Dreschmann, M.; Sander, O.; Klimm, A.; Roth, C.; Becker, J.
2013. 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, Darmstadt, Germany, 10-12 July, 2013, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ReCoSoC.2013.6581543
Parallelization and virtualization of genetic algorithms for sorting permutations by reversals
Soncco-Ãlvarez, J. L.; Almeida, G. M.; Becker, J.; Ayala-Rincon, M.
2013. 5th World Congress on Nature and Biologically Inspired Computing, NaBIC 2013, Fargo, North Dakota, USA, August 12 - 14, 2013, 29–35, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/NaBIC.2013.6617871
Coarse-grain optimization and code generation for embedded multicore systems
Goulas, G.; Valouxis, C.; Alefragis, P.; Voros, N. S.; Gogos, C.; Oey, O.; Stripf, T.; Bruckschloegl, T.; Becker, J.; El Moussawi, A.; Naullet, M.; Yuki, T.
2013. Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, 4-6 September 2013, Santander, Spain. Ed.: J. S. Matos, 379–386, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD.2013.48
A flexible implementation of the PSO algorithm for fine-and coarse-grained reconfigurable embedded systems
Rueckauer, M.; Munoz, D. M.; Stripf, T.; Oey, O.; Llanos, C. H.; Becker, J.
2013. 2013 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, Cancun, Mexico December 9-11, 2013. Ed.: R. Cumplido, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ReConFig.2013.6732293
Bringing Accuracy to Open Virtual Platforms (OVP): A Safari from High-Level Tools to Low-Level Microarchitectures
Shalina, G.; Bruckschloegl, T.; Figuli, p.; Tradowsky, C.; Almeida, G.; Becker, J.
2013. Proceedings on International Conference on Innovations In Intelligent Instrumentation, Optimization and Electrical Sciences, ICIIIOSP-2013, Dec. 2013, 22–27, Foundation of Computer Science
A New Approach to Model-Based Development for Audio Signal Processing
Tradowsky, C.; Figuli, P.; Seidenspinner, E.; Held, F.; Becker, J.
2013. 134th Audio Engineering Society Convention (AES’13), Rome, Italy, May 4-7, 2013 [Konferenz], 658–667, Curran
Hardware Supported Adaptive Data Collection for Networks on Chip
Heisswolf, J.; Weichslgartner, A.; Zaib, A.; Konig, R.; Wild, T.; Herkersdorf, A.; Teich, J.; Becker, J.
2013. IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW’13), Cambridge, Massachusetts/USA, May 20-24, 2013, 153–162, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IPDPSW.2013.124
Hybrid interconnect design for heterogeneous hardware accelerators
Pham-Quoc, C.; Heisswolf, J.; Werner, S.; Al-Ars, Z.; Becker, J.; Bertels, K.
2013. Design, Automation & Test in Europe Conference & Exhibition (DATE’13), Grenoble, France, March 18-22, 2013, 843–846, Institute of Electrical and Electronics Engineers (IEEE). doi:10.7873/DATE.2013.178
LImbiC: An adaptable architecture description language model for developing an application-specific image processor
Tradowsky, C.; Harbaum, T.; Deyerle, S.; Becker, J.
2013. IEEE Computer Society Annual Symposium on VLSI (ISVLSI’13), Natal, Brazil, August 5-7, 2013, 34–39, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISVLSI.2013.6654619
Simplify: A Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud
Marchesan Almeida, G.; Bellaver Longhi, O.; Bruckschloegl, T.; Hubner, M.; Hessel, F.; Becker, J.
2013. IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW’13), Cambridge, Massachusetts/USA, May 20-24, 2013, 2200–2205, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IPDPSW.2013.108
A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation
Roth, C.; Bucher, H.; Reder, S.; Buciuman, F.; Sander, O.; Becker, J.
2013. 26th Symposium on Integrated Circuits and Systems Design (SBCCI’13), Curitiba, Brazil, September 2-6, 2013, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SBCCI.2013.6644853
Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction
Roth, C.; Bucher, H.; Reder, S.; Sander, O.; Becker, J.
2013. 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC’13), Darmstadt, July 10-12, 2013, 1–8, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ReCoSoC.2013.6581524
A novel system on chip for software-defined, high-speed OFDM signal processing
Meyer, J.; Dreschmann, M.; Karnick, D.; Schindler, P. C.; Freude, W.; Leuthold, J.; Becker, J.
2013. 26th Symposium on Integrated Circuits and Systems Design (SBCCI’13), Curitiba, Brazil, September 2-6, 2013, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SBCCI.2013.6644883
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections
Zaib, A.; Heisswolf, J.; Weichslgartner, A.; Wild, T.; Teich, J.; Becker, J.; Herkersdorf, A.
2013. Euromicro Conference on Digital System Design (DSD’13), Los Alamitos, California/USA, September 4-6, 2013, 761–768, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DSD.2013.87
Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers
Heisswolf, J.; Bischof, S.; Ruckauer, M.; Becker, J.
2013. 26th Symposium on Integrated Circuits and Systems Design (SBCCI’13), Curitiba, Brazil, September 2-6, 2013, 1–6, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SBCCI.2013.6644857
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores
Figuli, P.; Tradowsky, C.; Gaertner, N.; Becker, J.
2013. International Symposium on System on Chip (SoC’13), Tampere, Finland, October 23-24, 2013, 1–8, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ISSoC.2013.6675270
Flexible WDM-PON with Nyquist-FDM and 31.25 Gbit/s per Wavelength Channel using Colorless, Low-Speed ONUs
Schindler, P. C.; Schmogrow, R. M.; Dreschmann, M.; Meyer, J.; Hillerkuss, D.; Tomkos, I.; Prat, J.; Krimmel, H.-.. G.; Pfeiffer, T.; Kourtessis, P.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
2013. Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC’13), Anaheim, CA, March 17-21, 2013, Article no 6533077, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1364/OFC.2013.OW1A.5
Demonstration of SOA-assisted open metro-access infrastructure for heterogeneous services
Schmuck, H.; Bonk, R.; Haslach, C.; Kuebart, W.; Karnick, D.; Meyer, J.; Poehlmann, W.; Fritzsche, D.; Weis, E.; Becker, J.; Freude, W.; Pfeiffer, T.
2013. 39th European Conference and Exhibition on Optical Communication (ECOC’13), London, United Kingdom, September 22-26, 2013, 3 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1049/cp.2013.1493
Dissertationen
Softwareframework für Prozessoren mit variablen Befehlssatzarchitekturen. Dissertation
Stripf, T.
2013. Karlsruher Institut für Technologie (KIT). doi:10.5445/IR/1000043813
Mixed-signal reconfigurable electronic system for industrial safety-critical applications. Dissertation
Girardey, R.
2013. Karlsruher Institut für Technologie (KIT)
A Problem-Oriented Approach for Dynamic Verification of Heterogeneous Embedded Systems. Dissertation
Mendoza Cervantes, F.
2013. KIT Scientific Publishing. doi:10.5445/KSP/1000038209
Using Fine Grain Approaches for highly reliable Design of FPGA-based Systems in Space. Dissertation
Niknahad, M.
2013. KIT Scientific Publishing. doi:10.5445/KSP/1000035134
Methoden zur Erstellung eines laufzeitadaptiven und zweidimensional rekonfigurierbaren Systems. Dissertation
Braun, L.
2013. Karlsruher Institut für Technologie (KIT)
2012
Zeitschriftenaufsätze
Processor Solutions for Smart Mobility
Becker, J.; Sander, O.; Roth, C.
2012. MPC, 48 (Juli), 1–8
HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture
Thomas, A.; Rückauer, M.; Becker, J.
2012. International Journal of Reconfigurable Computing, 2012, 832531. doi:10.1155/2012/832531
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices
Sander, O.; Glas, B.; Braun, L.; Müller-Glaser, K. D.; Becker, J.
2012. International Journal of Reconfigurable Computing, 2012, 219717. doi:10.1155/2012/219717
Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels
Roth, C.; Meyer, J.; Rueckauer, M.; Sander, O.; Becker, J.
2012. International Journal of Reconfigurable Computing, 2012, 729786/1–13. doi:10.1155/2012/729786
Adaptive Multiclient Network-on-Chip Memory Core : Hardware Architecture, Software Abstraction Layer, and Application Exploration
Göhringer, D.; Meder, L.; Werner, S.; Oey, O.; Becker, J.; Hübner, M.
2012. International journal of reconfigurable computing, 2012, Art.Nr. 298561. doi:10.1155/2012/298561
A Fault Tolerant Approach to Detect Transient Faults in Microprocessors Based on a Non-Intrusive Reconfigurable Hardware
Azambuja, J. R.; Pagliarini, S.; Altieri, M.; Kastensmidt, F. L.; Huebner-Glaser, M.; Becker, J.; Foucard, G.; Velazco, R.
2012. IEEE Transactions on Nuclear Science, 59 (4), 1117–1124. doi:10.1109/TNS.2012.2201750
Proceedingsbeiträge
A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems
Stripf, T.; Oey, O.; Bruckschloegl, T.; Koenig, R.; Becker, J.; Goulas, G.; Alefragis, P.; Voros, N. S.; Potman, J.; Sunesen, K.; Derrien, S.; Sentieys, O.
2012. 2012 IEEE 15th International Conference on Computational Science and Engineering (CSE 2012) : Paphos, Cyprus, 5 - 7 December 2012 ; [held in conjunction with the 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2012) and the 6th International Workshop on Ubiquitous Underwater Sensor Networks (UUWSN 2012) ; proceedings], 383–390, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/iccse.2012.60
From Scilab to multicore embedded systems: Algorithms and methodologies
Goulas, G.; Alefragis, P.; Voros, N. S.; Valouxis, C.; Gogos, C.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Goehringer, D.; Derrien, S.; Menard, D.; Sentieys, O.; Huebner, M.; Stripf, T.; Oey, O.; Becker, J.; Rauwerda, G.; Sunesen, K.; Kritharidis, D.; Mitas, N.
2012. 2012 International Conference on Embedded Computer Systems (SAMOS 2012) : Samos, Greece, 16 - 18 July 2012. Ed.: John McAllister, 268–275, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/samos.2012.6404184
From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach
Becker, J.; Stripf, T.; Oey, O.; Huebner, M.; Derrien, S.; Menard, D.; Sentieys, O.; Rauwerda, G.; Sunesen, K.; Kavvadias, N.; Masselos, K.; Goulas, G.; Alefragis, P.; Voros, N. S.; Kritharidis, D.; Mitas, N.; Goehringer, D.
2012. 2012 15th Euromicro Conference on Digital System Design (DSD 2012) : Cesme, Izmir, Turkey, 5 - 8 September 2012. Ed.: Smail Niar, 114–121, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/dsd.2012.65
On Designing Self-Aware Reconfigurable Platforms
Siozios, K.; Sidiropoulos, H.; Diamantopoulos, D.; Figuli, P.; Soudris, D.; Huebner, M.; Becker, J.
2012. 22nd International Conference on Field Programmable Logic and Applications (FPL 2012) : Oslo, Norway, 29 - 31 August 2012, 14–47, Institute of Electrical and Electronics Engineers (IEEE)
Hardware/Software Virtualization for the Reconfigurable Multicore Platform
Ferger, M.; Kadi, A.; Koedam, M.; Huebner, M.; Sinha, S.; Goossens, K.; Almeida, G.; Azambuja, J. R.; Becker, J.
2012. IEEE 15th International Conference on Computational Science and Engineering (CSE), 2012 : 5 - 7 Dec. 2012, Paphos, Cyprus ; [held in conjunction with] the 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC 2012) [and] the 6th International Workshop on Ubiquitous Underwater Sensor Networks (UUWSN 2012) ; proceedings, 341–344, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ICCSE.2012.54
Determination of On-Chip Temperature Gradients on Reconfigurable Hardware
Tradowsky, C.; Cordero, E.; Deuser, T.; Huebner, M.; Becker, J.
2012. 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), Cancun, Mexico, 5 - 7 December 2012, Art.Nr. 6416738, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ReConFig.2012.6416738
FPGA based System-on-Chip Solution for Compensation of aging Motor Parameters of two Phase Hybrid Stepper Motors
Dahm, N.; Hagner, M.; Huebner, M.; Becker, J.
2012. Embedded World 2012, Nuremberg, 28 February 2012 - 01 March 2012, 10 -, WEKA-Fachmedien
A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer
Roth, C.; Reder, S.; Sander, O.; Huebner, M.; Becker, J.
2012. Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques, Desenzano del Garda, Italy, March 19-23, 2012. Ed.: G. Riley, 202–207, ICST. doi:10.4108/icst.simutools.2012.247751
Hardware prototyping of novel invasive multicore architectures
Becker, J.; Friederich, S.; Heisswolf, J.; Koenig, R.; May, D.
2012. 17th Asia and South Pacific Design Automation Conference (ASP-DAC’12), Sydney, Australia, January 30 - February 2, 2012, 201–206, Institute of Electrical and Electronics Engineers (IEEE)
FPGA System-on-Chip Solution for a Field Oriented Hybrid Stepper Motor Control
Dahm, N.; Huebner, M.; Becker, J.
2012. 9th International Multi-Conference on Systems, Signals and Devices (SSD ’12), Chemnitz, March 20-23, 2012, 6 S., Institute of Electrical and Electronics Engineers (IEEE)
Realtime PCI Express Monitoring for Self Adaptive Reconfigurable Systems
Rueckauer, M.; Meyer, J.; Schubert, T.; Huebner, M.; Scheurer, D.; Becker, J.
2012. 9th International Multi-Conference on Systems, Signals and Devices (SSD ’12), Chemnitz, March 20-23, 2012, 6 S., Institute of Electrical and Electronics Engineers (IEEE)
On Dynamic Run-Time Processor Pipeline Reconfiguration
Tradowsky, C.; Thoma, F.; Huebner, M.; Becker, J.
2012. 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW’12), Shanghai, China, May 21-25, 2012; Vol. 1, 419–424, Institute of Electrical and Electronics Engineers (IEEE)
LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture
Tradowsky, C.; Thoma, F.; Huebner, M.; Becker, J.
2012. Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems (SIES’12), Karlsruhe, June 20-22, 2012, 279–282, Institute of Electrical and Electronics Engineers (IEEE)
A Scalable NoC Router Design Providing QoS Support using Weighted Round Robin Scheduling
Heisswolf, J.; Koenig, R.; Becker, J.
2012. Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications (ISPAW’12), Madrid, Spain, July 10-13, 2012, 625–632, Institute of Electrical and Electronics Engineers (IEEE)
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture
Stripf, T.; Koenig, R.; Becker, J.
2012. Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’12), Dresden, March 12-16, 2012. Ed.: K. Preas, 21–26, Institute of Electrical and Electronics Engineers (IEEE)
A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files
Stripf, T.; Koenig, R.; Becker, J.
2012. 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW’12), Shanghai, China, May 21-25, 2012; Vol. 1, 462–469, Institute of Electrical and Electronics Engineers (IEEE)
Adaptive Processor Architecture
Huebner, M.; Goehringer, D.; Tradowsky, C.; Henkel, J.; Becker, J.
2012. 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII), Samos, Greece, July 16-19, 2012, 244–251, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/SAMOS.2012.6404181
Ultra high speed digital down converter design for Virtex-6 FPGAs
Meyer, J.; Menzel, S.; Dreschmann, M.; Schmogrow, R.; Hillerkuss, D.; Freude, W.; Leuthold, J.; Becker, J.
2012. Proceedings of the 17th International OFDM Workshop (InOWo’12), Essen, August 29-30, 2012. Ed.: A. Czylwik, 151–155, VDE Verlag
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems
Werner, S.; Oey, O.; Goehringer, D.; Huebner, M.; Becker, J.
2012. Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’12), Dresden, March 12-16, 2012. Ed.: K. Preas, 280–283, Institute of Electrical and Electronics Engineers (IEEE)
Asynchronous Parallel MPSoC Simulation on the Single-chip Cloud Computer
Roth, C.; Reder, S.; Erdogan, G.; Sander, O.; Almeida, G.; Bucher, H.; Becker, J.
2012. 2012 International Symposium on System-on-Chip (SoC’12), Tampere, Finland, October 10-12, 2012, 8 S., Institute of Electrical and Electronics Engineers (IEEE)
Towards Design and Integration of a Vehicle-to-X based Adaptive Cruise Control
Sander, O.; Roth, C.; Glas, B.; Becker, J.
2012. Proceedings of the FISITA 2012 World Automotive Congress. Volume 12: Intelligent Transport System (ITS) & Internet of Vehicles, 87–99, Springer-Verlag
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures
Lemonnier, F.; Millet, P.; Almeida, G. M.; Hubner, M.; Becker, J.; Pillement, S.; Sentieys, O.; Koedam, M.; Sinha, S.; Goossens, K.; Piguet, C.; Morgan, M.-N.; Lemaire, R.
2012. 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XII), Samos, Greece, July 16-19, 2012, 228–235, Institute of Electrical and Electronics Engineers (IEEE)
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems
Stripf, T.; Oey, O.; Bruckschloegl, T.; Koenig, R.; Huebner, M.; Becker, J.; Goulas, G.; Alefragis, P.; Voros, N. S.; Rauwerda, G.; Sunesen, K.; Derrien, S.; Menard, D.; Sentieys, O.; Kavvadias, N.; Dimitroulakos, G.; Masselos, K.; Goehringer, D.; Perschke, T.; Kritharidis, D.; u. a.
2012. Proceedings of the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’12), York, United Kingdom, July 9-11, 2012. Ed.: L. S. Indrusiak, 8 S., Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/ReCoSoC.2012.6322879
Xilinx tools facilitate development of FPGA applications for IEC61508
Corradi, G.; Girardey, R.; Becker, J.
2012. 2012 NASA/ESA Conference on Adaptive Hardware and Systems (AHS’12), Erlangen, June 25-28, 2012, 54–61, Institute of Electrical and Electronics Engineers (IEEE)
Fine grain fault tolerance - A key to high reliability for FPGAs in space
Niknahad, M.; Sander, O.; Becker, J.
2012. 2012 IEEE Aerospace Conference, Big Sky, Montana, USA, March 3-10, 2012, 10 S., Institute of Electrical and Electronics Engineers (IEEE)
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS
Heisswolf, J.; Zaib, A.; Weichslgartner, A.; Koenig, R.; Wild, T.; Teich, J.; Herkersdorf, A.; Becker, J.
2012. 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW’12), Shanghai, China, May 21-25, 2012, 234–241, Institute of Electrical and Electronics Engineers (IEEE)
Framework for dynamic verification of multi-domain virtual platforms in industrial automation
Mendoza, F.; Pascal, J.; Nenninger, P.; Becker, J.
2012. 2012 IEEE 10th International Conference on Industrial Informatics (INDIN’12), Beijin, China, July 25-27, 2012, 935–940, Institute of Electrical and Electronics Engineers (IEEE)
On demand dependent deactivation of automotive ECUs
Schmutzler, C.; Simons, M.; Becker, J.
2012. Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE’12), Dresden, March 12-16, 2012. Ed.: K. Preas, 69–74, Institute of Electrical and Electronics Engineers (IEEE)
FPGA controlled DDS based frequency sweep generation of high linearity for FMCW radar systems
Ayhan, S.; Vu-Duy, V.; Pahl, P.; Scherr, S.; Huebner, M.; Becker, J.; Zwick, T.
2012. The 7th German Microwave Conference (GeMiC’12), Ilmenau, March 12-14, 2012, 4 S., Institute of Electrical and Electronics Engineers (IEEE)
Quality metrics for optical signals: Eye diagram, OSNR, Q-factor, EVM and BER
Freude, W.; Schmogrow, R.; Nebendahl, B.; Winter, M.; Josten, A.; Hillerkuss, D.; Koenig, S.; Meyer, J.; Dreschmann, M.; Huebner, M.; Koos, C.; Becker, J.; Leuthold, J.
2012. 14th International Conference on Transparent Optical Networks (ICTON’12), Coventry, United Kingdom, July 2-5, 2012, Vol. 1. Ed.: M. Jaworski, 21–24, Institute of Electrical and Electronics Engineers (IEEE)
Dissertationen
Mechanismen zur verteilten Selbstorganisation von adaptiver Hardware. Dissertation
Schuck, C.
2012. Karlsruher Institut für Technologie (KIT)
Grobgranular rekonfigurierbare Mikroarchitekturen zur dynamischen Erzeugung heterogener Prozessorinstanzen in Chip-Multiprozessoren. Dissertation
König, R.
2012. Karlsruher Institut für Technologie (KIT)
Hardwaregestützte Energieoptimierung von Elektrik/Elektronik-Architekturen durch adaptive Abschaltung von verteilten, eingebetteten Systemen. Dissertation
Schmutzler, C.
2012. KIT Scientific Publishing. doi:10.5445/KSP/1000028784
Hardwarenahe Simulation in SystemC zur Analyse dynamisch rekonfigurierbarer Systeme. Dissertation
Kühnle, M.
2012. Karlsruher Institut für Technologie (KIT)
Computing Architectures for Security Applications on Reconfigurable Hardware in Embedded Systems. Dissertation
Klimm, A.
2012. Karlsruher Institut für Technologie (KIT)
2011
Buchaufsätze
Two Dimensional Dynamic Multigrained Reconfigurable Hardware
Braun, L.; Becker, J.
2011. VLSI 2010 Annual Symposium : Selected papers. Ed. by Nikolaos Voros, 303–318, Springer Netherlands. doi:10.1007/978-94-007-1488-5_18
REFLECT: Rendering FPGAs to Multi-Core Embedded Computing
Cardoso, J. M. P.; Diniz, P. C.; Petrov, Z.; Bertels, K.; Hübner, M.; Van Someren, H.; Goncalves, F.; De Coutinho, J. G. F.; Constantinides, G. A.; Olivier, B.; Luk, W.; Becker, J.; Kuzmanov, G.; Thoma, F.; Braun, L.; Kühnle, M.; Nane, R.; Sima, V. M.; Kratky, K.; Alves, J. C.; u. a.
2011. Reconfigurable Computing-From FPGAs to Hardware/Software Codesign. Ed.: J. M. P. Cardoso, 261–290, Springer-Verlag. doi:10.1007/978-1-4614-0061-5_11
Smart Chips for Smart Surroundings - 4S
Schueler, E.; Koenig, R.; Becker, J.; Rauwerda, G.; Burgwal, M.; Smit, G.
2011. Reconfigurable Computing - From FPGAs to Hardware/Software Codesign. Ed.: J. M. P. Cardoso, 117–147, Springer-Verlag
Bücher
Multiprocessor System-on-Chip - Hardware Design and Tool Integration
Huebner, M.; Becker, J. (Hrsg.)
2011. Springer-Verlag
Zeitschriftenaufsätze
Exploration of Power-Performance Tradeoffs through Parameterization of FPGA-based Multiprocessor Systems
Goehringer, D.; Obie, J.; Braga, A.; Huebner, M.; Llanos, C.; Becker, J.
2011. International journal of reconfigurable computing, 2011, Art.Nr. 985931. doi:10.1155/2011/985931
A Security Scheme for Dependable Key Insertion in Mobile Embedded Devices
Klimm, A.; Glas, B.; Wachs, M.; Vogel, S.; Müller-Glaser, K. D.; Becker, J.
2011. International Journal of Reconfigurable Computing, 2011, 820454. doi:10.1155/2011/820454
Fast Startup for Xilinx FPGAs
Meyer, J.; Noguera, J.; Stewart, R.; Hübner, M.; Becker, J.
2011. Xcell Journal, (75), 18–23
Operating System for Runtime Reconfigurable Multiprocessor Systems
Goehringer, D.; Huebner, M.; Nguepi Zeutebouo, E.; Becker, J.
2011. International journal of reconfigurable computing, 2011, 121353/1–16. doi:10.1155/2011/121353
26 Tbit s-1 line-rate super-channel transmission utilizing all-optical fast Fourier transform processing
Hillerkuss, D.; Schmogrow, R.; Schellinger, T.; Jordan, M.; Winter, M.; Huber, G.; Vallaitis, T.; Bonk, R.; Kleinow, P.; Frey, F.; Roeger, M.; Koenig, S.; Ludwig, A.; Marculescu, A.; Li, J.; Hoh, M.; Dreschmann, M.; Meyer, J.; Ben Ezra, S.; Becker, J.; u. a.
2011. Nature photonics, 5 (6), 364–371. doi:10.1038/nphoton.2011.74
FPGA-Based Embedded Signal Processing for 3-D Ultrasound Computer Tomography
Birk, M.; Koehler, S.; Balzer, M.; Huebner, M.; Ruiter, N. V.; Becker, J.
2011. IEEE Transactions on Nuclear Science, 58 (4), 1647–1651. doi:10.1109/TNS.2011.2159017
Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems
Glas, B.; Sander, O.; Stuckert, V.; Müller-Glaser, K. D.; Becker, J.
2011. International Journal of Reconfigurable Computing, 2011, 836460/1–12. doi:10.1155/2011/836460
Evaluation of the reconfiguration of the data acquisition system for 3D USCT
Birk, M.; Hagner, C.; Balzer, M.; Ruiter, N. V.; Hübner, M.; Becker, J.
2011. International Journal of Reconfigurable Computing, 2011, 952937/1–9. doi:10.1155/2011/952937
Real-time OFDM transmitter beyond 100 Gbit/s
Schmogrow, R. M.; Winter, M.; Hillerkuss, D.; Nebendahl, B.; Ben-Ezra, S.; Meyer, J.; Dreschmann, M.; Huebner, M.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.
2011. Optics Express, 19 (13), 12740–12749. doi:10.1364/OE.19.012740
Reconfiguration Techniques for self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs
Schuck, C.; Haetzer, B.; Becker, J.
2011. International Journal of Reconfigurable Computing, 2011, 671546/1–12. doi:10.1155/2011/671546
Proceedingsbeiträge
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration
Meyer, J.; Noguera, J.; Huebner, M.; Braun, L.; Sander, O.; Gil, R. M.; Stewart, R.; Becker, J.
2011. Proceedings of the Design, Automation & Test in Europe (DATE’11), Grenoble, France, March 14-18, 2011, 1–6, Institute of Electrical and Electronics Engineers (IEEE)
HLA-based Simulation Environment for distributed SystemC Simulation
Roth, C.; Sander, O.; Kuehnle, M.; Becker, J.
2011. Proceedings of the 4th International ICST Conference on Simulation Tools and Techniques (SIMUTools’11), Barcelona, Spain, March 21-25, 2011, 108–114, ICST
Modular Framework for Multi-level Multi-device MPSoC Simulation
Roth; Sander, O.; Almeida, G.; Ost, L.; Hebert, N.; Sassatelli, G.; Benoit, P.; Torres, L.; Becker, J.
2011. Proceedings of the IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW’11), Anchorage, Alaska, USA, May 16-20, 2011, 136–142, Institute of Electrical and Electronics Engineers (IEEE)
Towards Provable Protocol Conformance of Serial Automotive Communication IP
Becker, J. E.; Sander, O.; Klimm, A.; Bulach, S.; Weinberger, K.; Becker, J.
2011. Proceedings of the Design & Verification Conference & Exhibition (DVCon’11), San Jose, California, USA, February 28 - March 3, 2011, 1P.5/1–6, MPA
A heterogeneous SoC Architecture with embedded virtual fpga Cores and Runtime core Fusion
Figuli, P.; Hübner, M.; Girardey, R.; Bapp, F.; Bruckschloegl, T.; Thoma, F.; Henkel, J.; Becker, J.
2011. Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, San Diego, California, USA, June 6-9, 2011, 96–103, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/AHS.2011.5963922
101.5 Gbit/s Real-Time OFDM Transmitter with 16QAM Modulated Subcarriers
Schmogrow, R.; Nebendahl, B.; Hillerkuss, D.; Meyer, J.; Dreschmann, M.; Huebner, M.; Becker, J.; Koos, C.; Freude, W.; Leuthold, J.; Winter, M.
2011. Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC 2011), Los Angeles, California, USA, March 6-10, 2011, 2346–2348, Institute of Electrical and Electronics Engineers (IEEE)
Run-Time Resource Instantiation for Fault Tolerance in FPGAs
Pereira, M.; Braun, L.; Huebner, M.; Becker, J.; Carro, L.
2011. Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems (AHS’11), San Diego, California, USA, June 6-9, 2011, 88–95, Institute of Electrical and Electronics Engineers (IEEE)
Implementation of an ultra-high speed 256-point FFT for Xilinx Virtex-6 devices
Dreschmann, M.; Meyer, J.; Huebner, M.; Schmogrow, R.; Hillerkuss, D.; Becker, J.; Leuthold, J.; Freude, W.
2011. Proceedings of the IEEE 9th International Conference on Industrial Informatics (INDIN’11), Caparica, Lisbon, Portugal, July 26-29, 2011, 829–834, Institute of Electrical and Electronics Engineers (IEEE)
Flexible and Efficient Co-Simulation of Networked Embedded Devices
Roth, C.; Sander, O.; Kuehnle, M.; Becker, J.
2011. Proceedings of the Twenty-Fourth Symposium on Integrated Circuits and Systems Design, Joao Pessoa, Brazil, August 30 - September 02, 2011, 61–66, Association for Computing Machinery (ACM)
The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip
Kuehnle, M.; Brito, A.; Roth, C.; Dagas, K.; Becker, J.
2011. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI’11), Chennai, India, July 4-6, 2011, 13–18, IEEE Computer Society
Embedded Systems Start-up under Timing Constraints on Modern FPGAs
Meyer, J.; Noguera, J.; Huebner, M.; Stewart, R.; Becker, J.
2011. Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL’11), Chania, Crete, Greece, September 5-7, 2011. Ed.: P. Athanas, 103–109, Institute of Electrical and Electronics Engineers (IEEE)
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture
Huebner, M.; Figuli, P.; Girardey, R.; Soudris, D.; Siozos, K.; Becker, J.
2011. Proceedings of the 18th Reconfigurable Architectures Workshop (RAW’11), Anchorage, Alaska, USA, May 16-17 2011, 143–149, Institute of Electrical and Electronics Engineers (IEEE)
An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels
Kuehnle, M.; Brito, A. V.; Roth, C.; Kruesselin, M.; Becker, J.
2011. Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’11), Montpellier, France, June 20-22, 2011. Ed.: L. S. Indrusiak, 1–8, Institute of Electrical and Electronics Engineers (IEEE)
A statistical power estimation methodology embedded in a SystemC code translator
Kuehnle, M.; Wagner, A.; Becker, J.
2011. Proceedings of the Twenty-Fourth Symposium on Integrated Circuits and Systems Design, Joao Pessoa, Brazil, August 30 - September 2, 2011, 79–84, Association for Computing Machinery (ACM)
Architecture Design Space Exploration of Run-Time Scalable Issue-Width Processors
Koenig, R.; Stripf, T.; Heisswolf, J.; Becker, J.
2011. Proceedings of the International Conference on Embedded Computer Systems (SAMOS’11), Samos, Greece, July 18-21, 2011. Ed.: L. Carro, 77–84, Institute of Electrical and Electronics Engineers (IEEE)
A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors
Koenig, R.; Stripf, T.; Heisswolf, J.; Becker, J.
2011. Proceedings of the IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW’11), Anchorage, Alaska, USA, May 16-20, 2011, 150–157, Institute of Electrical and Electronics Engineers (IEEE)
A study on fine granular fault tolerance methodologies for FPGAs
Niknahad, M.; Sandery, O.; Becker, J.
2011. Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’11), Montpellier, France, June 20-22, 2011. Ed.: L. S. Indrusiak, 1–5, Institute of Electrical and Electronics Engineers (IEEE)
QFDR-an integration of Quadded Logic for modern FPGAs to tolerate high radiation effect rates
Niknahad, M.; Sandery, O.; Becker, J.
2011. Proceedings of the 12th European Conference on Radiation and its Effects on Component and Systems (RADECS’11), Sevilla, Spain, September 19-23, 2011 RADECS 2011, 119–122, Institute of Electrical and Electronics Engineers (IEEE)
FGTMR - Fine Grain Redundancy Method for Reconfigurable Architectures under high Failure Rates
Niknahad, M.; Sandery, O.; Becker, J.
2011. The 16th North-East Asia Symposium on Nano, Information Technology and Reliability (NASNIT’11), Macao, China, October 24-26 2011, Ed.: H. Chi Tin, 186–191, Institute of Electrical and Electronics Engineers (IEEE)
Using Quadded Logic in nanoPLAs to aggressively increase circuit yield
Niknahad, M.; Sandery, O.; Carro, L.; Azambuja, J.; Becker, J.; KastenSmidt, F. L.
2011. The 16th North-East Asia Symposium on Nano, Information Technology and Reliability (NASNIT’11), Macao, China, October 24-26, 2011. Ed.: H. Chi Tin, 180–185, Institute of Electrical and Electronics Engineers (IEEE)
All-optical real-time OFDM transmitter and receiver
Freude, W.; Hillerkuss, D.; Schellinger, T.; Schmogrow, R.; Winter, M.; Vallaitis, T.; Bonk, R.; Marculescu, A.; Li, J.; Dreschmann, M.; Meyer, J.; Ben Ezra, S.; Caspi, M.; Nebendahf, B.; Parmigiani, F.; Petropoiu, P.; Resan, B.; Oehler, A.; Weingarten, K.; Becker, J.; u. a.
2011. Conference on Lasers and Electro-Optics (CLEO’11), Baltimore, Maryland, USA, May 1-6, 2011, 1–2, Institute of Electrical and Electronics Engineers (IEEE)
Approach of an FPGA based adaptive stepper motor control system
Dahm, N.; Huebner, M.; Becker, J.
2011. Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’11), Montpellier, France, June 20-22, 2011. Ed.: L. S. Indrusiak, 1–6, Institute of Electrical and Electronics Engineers (IEEE)
RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC
Goehringer, D.; Werner, S.; Huebner, M.; Becker, J.
2011. Proceedings of the 21st International Conference on Field Programmable Logic and Applications (FPL’11), Chania, Crete, Greece, September 5-7, 2011. Ed.: P. Athanas, 181–184, Institute of Electrical and Electronics Engineers (IEEE)
Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip
Goehringer, D.; Oey, O.; Huebner, M.; Becker, J.
2011. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS’11), Samos, Greece, July 18-21, 2011. Ed.: L. Carro, 380–387, Institute of Electrical and Electronics Engineers (IEEE)
Reconfigurable MPSoC versus GPU: Performance, power and energy evaluation
Göhringer, D.; Birk, M.; Dasse-Tiyo, Y.; Ruiter, N.; Hübner, M.; Becker, J.
2011. Proceedings of the 9th IEEE International Conference on Industrial Informatics (INDIN’11), Lisbon, Portugal, July 26-29, 2011, 848–853, Institute of Electrical and Electronics Engineers (IEEE)
New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach
Goehringer, D.; Becker, J.
2011. VLSI 2010 Annual Symposium. Selected papers. Ed.: N. Voros, 335–346, Springer-Verlag
Adaptive Multi-Client Network-on-Chip Memory
Goehringer, D.; Meder, L.; Huebner, M.; Becker, J.
2011. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig’11), Cancun, Mexico, November 30 - December 2, 2011. Ed.: P. Athanas, 7–12, Institute of Electrical and Electronics Engineers (IEEE)
A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors
Stripf, T.; Koenig, R.; Becker, J.
2011. International Conference on Embedded Computer Systems (SAMOS 2011), Samos, Greece, July 18 - 21, 2011. Ed.: L. Carro, 157–164, Institute of Electrical and Electronics Engineers (IEEE)
Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs
Schuck, C.; Haetzer, B.; Huebner, M.; Becker, J.
2011. Proceedings of the IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW’11), Anchorage, Alaska, USA, May 16-20, 2011, 181–188, Institute of Electrical and Electronics Engineers (IEEE)
Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing
Birk, M.; Guth, A.; Zapf, M.; Balzer, M.; Ruiter, N.; Hübner, M.; Becker, J.
2011. Conference on Design & Architectures for Signal & Image Processing (DASIP 2011), Tampere, Finland, November 2-4, 2011. Ed.: A. Morawiec, 67–74, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/DASIP.2011.6136856
A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker
Ruemmele-Werner, M.; Perschke, T.; Braun, L.; Huebner, M.; Becker, J.
2011. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS’11), Rio de Janeiro, Brazil, May 15-18, 2011, 853–856, Institute of Electrical and Electronics Engineers (IEEE)
Power and performance optimization through MPI supported dynamic voltage and frequency scaling
Thoma, F.; Hübner, M.; Göhringer, D.; Yilmaz, H. Ü.; Becker, J.
2011. 3rd Many-core Applications Research Community (MARC) Symposium. Ed.: D. Göhringer, 75–78, KIT Scientific Publishing
Proceedingsbände
3rd Many-core Applications Research Community (MARC) Symposium. (KIT Scientific Reports ; 7598)
Göhringer, D.; Hübner, M.
2011. (J. Becker, Hrsg.), KIT Scientific Publishing. doi:10.5445/KSP/1000023937
2010
Buchaufsätze
Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support
Goehringer, D.; Huebner, M.; Becker, J.
2010. Multiprocessor System-on-Chip - Hardware Design and Tool Integration. Ed.: M. Hübner, 127–154, Springer-Verlag
Zeitschriftenaufsätze
Real-Time Software-Defined Multiformat Transmitter Generating 64QAM at 28 GBd
Becker, J.; Dreschmann, M.; Huebner, M.; Meyer, J.; Schmogrow, R.; Hillerkuss, D.; Winter, M.; Nebendahl, B.; Koos, C.; Freude, W.; Leuthold, J.
2010. IEEE Photonics Technology Letters, 22 (21), 1601–1603. doi:10.1109/LPT.2010.2073698
Car-to-X Simulation Environment for Comprehensive Design Space Exploration Verification and Test
Becker, J.; Roth, C.; Sander, O.; Huebner, M.
2010. SAE International Journal of Passenger Cars - Electronic and Electrical Systems, 3 (1), 17–26. doi:10.4271/2010-01-0451
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
Kepa, K.; Morgan, F.; Kosciuszkiewicz, K.; Braun, L.; Huebner, M.; Becker, J.
2010. ACM transactions on reconfigurable technology and systems : TRETS, 4 (1). doi:10.1145/1857927.1857931
Proceedingsbeiträge
Orthogonal frequency division multiplexing (OFDM) in photonic communications
Freude, W.; Hillerkuss, D.; Schellinger, T.; Schmogrow, R.; Winter, M.; Vallaitis, T.; Bonk, R.; Marculescu, A.; Dreschmann, M.; Meyer, J.; Ezra, S. B.; Narkiss, N.; Nebendahl, B.; Parmigiani, F.; Petropoulos, P.; Resan, B.; Weingarten, K.; Ellermeyer, T.; Lutz, J.; Becker, J.; u. a.
2010. Photonics 2010 : Tenth International Conference on Fiber Optics and Photonics : 11 - 15 December 2010, Guwahati, India, SPIE
Orthogonal frequency division multiplexing (OFDM) in photonic communications
Freude, W.; Hillerkuss, D.; Schellinger, T.; Schmogrow, R.; Winter, M.; Vallaitis, T.; Bonk, R.; Marculescu, A.; Dreschmann, M.; Meyer, J.; Ezra, S. B.; Narkiss, N.; Nebendahl, B.; Parmigiani, F.; Petropoulos, P.; Resan, B.; Weingarten, K.; Ellermeyer, T.; Lutz, J.; Becker, J.; u. a.
2010. Photonics 2010 : Tenth International Conference on Fiber Optics and Photonics : 11 - 15 December 2010, Guwahati, India, SPIE
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration
Meyer, J.; Huebner, M.; Braun, L.; Sander, O.; Noguera, J.; Stewart, R.; Becker, J.
2010. VLSI 2010-Annual Symposium. Selected papers. Ed.: N. Voros, 289–302, Springer-Verlag
Performance, Accuracy, Power Consumption and Resource Utilization Analysis for Hardware / Software realized Artificial Neural Networks
Braga, A.; Goehringer, D.; Llanos, C.; Obie, J.; Huebner, M.; Becker, J.
2010. Proceedings of the Fifth International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2010), Liverpool, UK, 8-10 September, 2010, 1629–1636, Institute of Electrical and Electronics Engineers (IEEE)
Semi-Automatic Toolchain for Reconfigurable Multiprocessor Systems-on-Chip: Architecture Development and Application Partitioning
Becker, J.; Goehringer, D.; Huebner, M.; Benz, M.
2010. Proceedings of the Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2010), Monterey, California, USA, February 21 - 23, 2010, 286, Association for Computing Machinery (ACM)
CAP-OS: Operating System for Runtime Scheduling, Task Mapping and Resource Management on Reconfigurable Multiprocessor Architectures
Becker, J.; Huebner, M.; Goehringer, D.; Zeutebouo, E. N.
2010. Proceedings of the 2010 IEEE International Symposium on Parallel & Distributed Processing workshops and Phd forum, IPDPSW, Atlanta, Georgia, USA, 19 - 23 April 2010, 1 S., Institute of Electrical and Electronics Engineers (IEEE)
Fast dynamic and partial reconfiguration Data Path with low Hardware overhead on Xilinx FPGAs
Becker, J.; Huebner, M.; Goehringer, D.; Noguera, J.
2010. Proceedings of the 2010 IEEE International Symposium on Parallel & Distributed Processing workshops and Phd forum, IPDPSW, Atlanta, Georgia, USA, 19 - 23 April 2010, 1 S., Institute of Electrical and Electronics Engineers (IEEE)
KAHRISMA: A Novel Hypermorphic Reconfigurable- Instruction-Set Multi-grained-Array Architecture
Becker, J.; Koenig, R.; Stripf, T.; Bauer, L.; Henkel, J.; Shafique, M.; Ahmed, W.
2010. Proceedings of the 2010 Design, Automation & Test in Europe Conference & Exhibition, DATE 2010, Dresden, Germany, 8 - 12 March 2010, Vol. 1, 819–824, Institute of Electrical and Electronics Engineers (IEEE)
A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip
Becker, J.; Goehringer, D.; Huebner, M.; Benz, M.
2010. Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, proceedings, FCCM 2010, 2-4 May 2010, Charlotte, North Carolina, USA. Ed.: K. L. Pocek, 259, IEEE Computer Society
High Performance Reconfigurable Multi-Processor-Based Computing on FPGAs
Becker, J.; Goehringer, D.
2010. Proceedings of the 2010 IEEE International Symposium on Parallel & Distributed Processing workshops and Phd forum, IPDPSW, Atlanta, Georgia, USA, 19 - 23 April 2010, 4 S., Institute of Electrical and Electronics Engineers (IEEE)
Fast Sequential FPGA Startup based on Partial and Dynamic Reconfiguration
Becker, J.; Huebner, M.; Meyer, J.; Sander, O.; Braun, L.; Noguera, J.; Stewart, R.
2010. Proceedings of the IEEE Annual Symposium on VLSI, ISVLSI 2010, Lixouri, Kefalonia, Greece, 5-7 July 2010, 190–194, Institute of Electrical and Electronics Engineers (IEEE)
Reliability Analysis and Improvement in Nano Scale Design
Becker, J.; Huebner, M.; Niknahad, M.
2010. Proceedings of the IEEE Annual Symposium on VLSI, ISVLSI 2010, Lixouri, Kefalonia, Greece, 5-7 July 2010, 299–303, Institute of Electrical and Electronics Engineers (IEEE)
FPGA-based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications
Becker, J.; Goehringer, D.
2010. Proceedings of the IEEE Annual Symposium on VLSI, ISVLSI 2010, Lixouri, Kefalonia, Greece, 5-7 July 2010, 477–478, Institute of Electrical and Electronics Engineers (IEEE)
FPGA-based Embedded Signal Processing for 3D Ultrasound Computer Tomography
Becker, J.; Birk, M.; Koehler, S.; Balzer, M.; Huebner, M.; Ruiter, N.
2010. Proceedings of the 17th IEEE-NPSS Real Time Conference (RT), Lisbon, Portugal, 24-28 May 2010, 1–5, Institute of Electrical and Electronics Engineers (IEEE)
Message Passing Interface Support for the Runtime Adaptive Multi-Processor System-on-Chip RAMPSoC
Becker, J.; Goehringer, D.; Huebner, M.; Hugot-Derville, L.
2010. Proceedings of the 10th International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2010, Samos, Greece, 19-22 July, 2010. Ed.: F. J. Kurdahi, 357–364, Institute of Electrical and Electronics Engineers (IEEE)
Scenario extraction for a refined timing-analysis of automotive network topologies
Becker, J.; Traub, M.; Streichert, T.; Krasovytskyy, O.
2010. Proceedings of the 2010 Design, Automation & Test in Europe Conference & Exhibition, DATE 2010, Dresden, Germany, 8 - 12 March 2010, 81–86, Institute of Electrical and Electronics Engineers (IEEE)
Debugging Sequential Logic on FPGAs using Internal Configuration Access Port
Becker, J.; Müller-Glaser, K. D.; Schwalb, T.; Braun, L.; Werner, S.; Huebner, M.
2010. Conference on System Software, SoC and Silicon Debug (S4D 2010), Southampton, UK, September 15-16, 2010
Car-to-X-in-the-Loop - Development Environment for Vehicles, Control Units and Communication Systems in the Context of future Mobility Concepts
Becker, J.; Müller-Glaser, K. D.; Roth, C.; Sander, O.; Düser, T.; Glas, B.; Seifermann, A.; Albers, A.; Henning, J.
2010. 26. VDI-VW-Gemeinschaftstagung Fahrerassistenz und Integrierte Sicherheit, Tagung Wolfsburg, 6. und 7. Oktober 2010, VDI Verlag
A Flexible Integrated Cryptoprocessor for Authentication Protocols based on Hyperelliptic Curve Cryptography
Becker, J.; Klimm, A.; Haas, M.; Sander, O.
2010. Proceedings of the 2010 International Symposium on System on Chip (SoC), Tampere, 29-30 Sept. 2010, 35–42, Institute of Electrical and Electronics Engineers (IEEE)
Two-Dimensional Dynamic Multigrained Reconfigurable Hardware
Becker, J.; Braun, L.
2010. Proceedings of the 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Lixouri, Kefalonia, 5-7 July 2010, 475–476, Institute of Electrical and Electronics Engineers (IEEE)
A Secure Keyflashing Framework for Access Systems in Highly Mobile Devices
Becker, J.; Klimm, A.; Glas, B.; Wachs, M.; Müller-Glaser, K. D.
2010. Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC’10 - May 17-19, 2010 Karlsruhe, Germany. Ed.: M. Hübner, 121–126, KIT Scientific Publishing
ECDSA Signature Processing over Prime Fields for Reconfigurable Embedded Systems
Becker, J.; Sander, O.; Glas, B.; Stuckert, V.; Müller-Glaser, K. D.
2010. Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC’10 - May 17-19, 2010 Karlsruhe, Germany. Ed.: M. Hübner, 115–120, KIT Scientific Publishing
First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography
Becker, J.; Huebner, M.; Birk, M.; Hagner, C.; Balzer, M.; Ruiter, N.
2010. Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC’10 - May 17-19, 2010 Karlsruhe, Germany. Ed.: M. Hübner. 5th International Workshop on Reconfigurable Communication-centric Systems on Chip (ReCoSoC’10 2010) Karlsruhe, Deutschland, 17.05.2010–19.05.2010, 109–114, KIT Scientific Publishing. doi:10.5445/IR/1000018653
ISRC: a runtime system for heterogeneous reconfigurable architectures
Becker, J.; Thoma, F.
2010. Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC’10 - May 17-19, 2010 Karlsruhe, Germany. Ed.: M. Hübner, 59–66, KIT Scientific Publishing
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/Virtex II-Pro FPGAs: A Case Study of Distributed Power Management
Becker, J.; Schuck, C.; Haetzer, B.
2010. Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC’10 - May 17-19, 2010 Karlsruhe, Germany. Ed.: M. Hübner, 45–50, KIT Scientific Publishing
Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors
Becker, J.; Huebner, M.; Goehringer, D.; Obie, J.
2010. Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC’10 - May 17-19, 2010 Karlsruhe, Germany. Ed.: M. Hübner, 13–20, KIT Scientific Publishing
Dissertationen
A Flexible Framework for Hardware/Software Design Space Exploration using Rewriting-Logic. Dissertation
Morra, C. F.
2010. Karlsruher Institut für Technologie (KIT)
Durchgängige Timing-Bewertung von Vernetzungsarchitekturen und Gateway-Systemen im Kraftfahrzeug. Dissertation
Traub, M.
2010. KIT Scientific Publishing. doi:10.5445/KSP/1000020379
2009
Buchaufsätze
Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies
Becker, J.; Müller-Glaser, K. D.; Braun, L.; Schwalb, T.; Graf, P.; Huebner, M.; Ullmann, M.
2009. Dynamically reconfigurable systems: architectures, design methods and applications. Ed.: M. Platzner, 245–268, Springer-Verlag
Control of dynamic reconfiguration
Thoma, F.; Becker, J.
2009. Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach. Ed.: N. Voros, 129–137, Springer-Verlag
Training
Huebner, M.; Becker, J.; Kuehnle, M.; Thoma, F.
2009. Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach. Ed.: N. Voros, 233–249, Springer-Verlag
The MORPHEUS Data Communication And Storage Infrastructure
Kühnle, M.; Hübner, M.; Becker, J.; u. a.
2009. Dynamic system reconfiguration in heterogeneous platforms. The MORPHEUS approach. Ed.: N. S. Voros, 93–105, Springer-Verlag
Zeitschriftenaufsätze
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
Becker, J.; Huebner, M.; Braun, L.; Kepa, K.; Morgan, F.; Kosciuszkiewicz, K.
2009. ACM Transactions on Reconfigurable Technology and Systems, 4 (1), 4/1–26
An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing
Becker, J.; Schuck, C.; Haetzer, B.
2009. International Journal of Reconfigurable Computing, 2009, 273791/1–11
A Taxonomy of Reconfigurable Single/Multi-Processor Systems-on-Chip
Huebner, M.; Becker, J.; Goehringer, D.; Perschke, T.
2009. International Journal of Reconfigurable Computing, 2009, 395018/1–11
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture
Braun, L.; Goehringer, D.; Huebner, M.; Becker, J.; Perschke, T.; Schatz, V.
2009. Journal of Real-Time Image Processing, 4 (2), 109–125
Proceedingsbeiträge
Image Processing exploiting new dimensions in reconfigurable multiprocessor systems (Invited Talk)
Goehringer, D.; Perschke, T.; Becker, J.
2009. Design, Automation & Test in Europe Conference & Exhibition : DATE 2009, Nice, France, 20 - 24 April 2009, Institute of Electrical and Electronics Engineers (IEEE)
Multi-Processor-based High Performance Computing utilizing dynamic reconfigurable Hardware (PhD Poster)
Goehringer, D.; Becker, J.
2009. Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’09, 20 - 24 April 2009, Nice, France, Art.Nr.: 5470800, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IPDPSW.2010.5470800
Car-to-X Kommunikation auf vertrauenswürdiger rekonfigurierbarer Hardware
Glas, B.; Sander, O.; Mueller-Glaser, K. D.; Becker, J.
2009. 25. VDI/VW Gemeinschaftstagung Automotive Security, VDI Verlag
Star-wheels network-on-chip featuring a self-adaptive mixed topology and a synergy of a circuit- and a packet-switching communication protocol
Goehringer, D.; Liu, B.; Huebner, M.; Becker, J.
2009. 19th International Conference on Field Programmable Logic and Applications; Prague, Czech Republic, 31 August 2009 through 2 September 2009, 320–325, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/FPL.2009.5272279
System concept for an FPGA based real-time capable automotive ECU simulation system
Becker, J.; Sander, O.; Roth, C.; Stuckert, V.
2009. Proceedings of the SBCCI ’09 22nd Symposium on Integrated Circuits and System Design, Natal, Brazil, August 31 - September 03, 2009, 34/1–6, Association for Computing Machinery (ACM)
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip
Becker, J.; Koenig, R.; Dreschmann, M.; Huebner, M.
2009. Proceedings of the 2009 International Symposium on System-on-Chip, (SOC 2009), Tampere, Finland, 5 - 7 October 2009. Ed.: J. Nurmi, 110–113, Institute of Electrical and Electronics Engineers (IEEE)
Sicherung von Zuverlässigkeit und Interoperabilität bei der fahrzeuginternen Kommunikation mittels formaler Verifikation
Becker, J.; Sander, O.; Klimm, A.; Becker, J. E.; Kimmeskamp, T.; Formann, J.; Echtle, K.; Weinberger, K.; Bulach, S.
2009. Proceedings of the 14. Internationaler Kongress Elektronik im Kraftfahrzeug = Electronic Systems for Vehicles, Baden-Baden, 7. und 8. Oktober 2009, 345–356, VDI Verlag
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs
Becker, J.; Klimm, A.; Sander, O.
2009. Proceedings of the 2009 IEEE International Symposium on Parallel & Distributed Processing, (IPDPS 2009), Rome, Italy, 23 - 29 May 2009, 1–8, Institute of Electrical and Electronics Engineers (IEEE)
Design of a Vehicle-to-Vehicle Communication System on Reconfigurable Hardware
Mueller-Glaser, K. D.; Becker, J.; Sander, O.; Glas, B.; Roth, C.
2009. Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, 9 - 11 December 2009. Ed.: N. Bergmann, 14–21, Institute of Electrical and Electronics Engineers (IEEE)
GenerateRCS: A High-Level Design Tool for Generating Reconfigurable Computing Systems
Becker, J.; Goehringer, D.; Luhmann, J.
2009. Proceedings / VLSI-SoC: Advanced Topics on Systems on a Chip. A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA. Ed.: P. Hasler, Springer US
Method for improving performance in online routing of reconfigurable nano architectures
Becker, J.; Huebner, M.; Niknahad, M.
2009. Proceedings of the 2009 IEEE International SOC Conference (SOCC 2009), Belfast, Ireland, 9 - 11 September 2009, 65–70, Institute of Electrical and Electronics Engineers (IEEE)
A Multi-Core Signal Processor for Heterogeneous Reconfigurable Computing
Kuehnle, M.; Huebner, M.; Becker, J.; u. a.
2009. International Symposium on System-on-Chip (SOC 2009), October 5-7, 2009, Tampere, Finland, 106–109, Institute of Electrical and Electronics Engineers (IEEE)
Car-to-X Kommunikation auf vertrauenswürdiger rekonfigurierbarer Hardware
Glas, B.; Sander, O.; Mueller-Glaser, K. D.; Becker, J.
2009. Automotive Security - 25. VDI/VW-Gemeinschaftstagung, 19. und 20. Oktober 2009, Ingolstadt, Germany; 1 CD-Rom, VDI-Wissensforum
Dynamic Reconfigurable Mixed-Signal Architecture for Safety Critical Applications
Girardey, R.; Hübner, M.; Becker, J.
2009. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2009), 31. Aug. - 2.Sept. 2009, Prague, Czech Republic, 503–506, Institute of Electrical and Electronics Engineers (IEEE)
Real time information processing for car to car communication applications
Sander, O.; Glas, B.; Roth, C.; Becker, J.; Mueller-Glaser, K. D.
2009. EAEC 2009 - Europe in the second century of auto-mobility, 12th EAEC European Automotive Congress, June 29 to July 1, 2009, Bratislava, Slovakia; 1 CD-ROM, Bratislava
Configuration Measurement for FPGA-based Trusted Platforms
Glas, B.; Klimm, A.; Mueller-Glaser, K. D.; Becker, J.
2009. IEEE/IFIP International Symposium on Rapid System Prototyping (RSP 2009), 23-26 June 2009, Paris, France, 123–129, Institute of Electrical and Electronics Engineers (IEEE)
Testing of an FPGA-based C2X-Communication Prototype with a Model Based Traffic Generation
Sander, O.; Glas, B.; Roth, C.; Becker, J.; Mueller-Glaser, K. D.
2009. IEEE/IFIP International Symposium on Rapid System Prototyping (RSP 2009), 23-26 June 2009, Paris, France, 68–71, Institute of Electrical and Electronics Engineers (IEEE)
Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol
Göhringer, D.; Liu, B.; Hübner, M.; Becker, J.
2009. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL 2009), 31. Aug. - 2. Sept. 2009, Prague. Czech Republic, 320–325, Institute of Electrical and Electronics Engineers (IEEE)
Priority-based packet communication on a bus-shaped structure for FPGA-systems
Sander, O.; Glas, B.; Roth, C.; Becker, J.; Mueller-Glaser, K. D.
2009. DATE 2009 - Design, Automation & Test in Europe Conference & Exhibition, 20-24 April 2009, Nice, France, 178–183, Institute of Electrical and Electronics Engineers (IEEE)
Multi-Processor-based High Performance Computing utilizing dynamic reconfigurable Hardware
Becker, J.; Göhringer, D.
2009. DATE 2009 - Design, Automation & Test in Europe Conference & Exhibition, 20 - 24 April 2009, Nice, France; PH.D. Forum, Institute of Electrical and Electronics Engineers (IEEE)
Car-to-Car Communication Security on Reconfigurable Hardware
Glas, B.; Sander, O.; Stuckert, V.; Mueller-Glaser, K. D.; Becker, J.
2009. Proceedings / 2009 IEEE Vehicular Technology Conference (VTC 2009 Spring), 26 - 29 April 2009, Barcelona, Spain, 5 S., Institute of Electrical and Electronics Engineers (IEEE)
Image Processing exploiting new dimensions in reconfigurable multiprocessor systems
Göhringer, D.; Perschke, T.; Becker, J.
2009. DATE 2009 - Design, Automation & Test in Europe Conference & Exhibition, 20 - 24 April 2009, Nice, France; Friday Workshop, Institute of Electrical and Electronics Engineers (IEEE)
Dissertationen
Power Optimized Design of FPGA-based Self Adaptive Systems. Dissertation
Paulsson, K.
2009. Universität Karlsruhe (TH)
2008
Buchaufsätze
A System Architecture for Reconfigurable Trusted Platforms
Glas, B.; Klimm, A.; Sander, O.; Mueller-Glaser, K. D.; Becker, J.
2008. DATE 2008 - Design, Automation and Test in Europe, 10 - 14 March 2008, Munich, Germany, 541–544, IEEE Service Center
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor
Kuehnle, M.; Ries, F.; Huebner, M.; Becker, J.; u. a.
2008. DATE 2008 - Design, automation and test in Europe, 10 - 14 March 2008, Munich, Germany, 1352–1357, IEEE Service Center
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms
Koenig, R.; Stripf, T.; Becker, J.
2008. DATE 2008 - Design, Automation and Test in Europe, 10 - 14 March 2008, Munich, Germany, 604–609, IEEE Service Center
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs
Paulsson, K.; Huebner, M.; Becker, J.
2008. DATE 2008 - Design, Automation and Test in Europe, 10 - 14 March 2008, Munich, Germany, 50–55, IEEE Service Center
Standards for Electric/Electronic Components and Architectures
Becker, J.; Sander, O.; Huebner, M.; Traub, M.; Weber, T.; Luka, J.; Lauer, V.
2008. Convergence 2008, Oct 20-22, 2008, Detroit, Michigan, USA, Detroit
Data Reallocation by Exploiting FPGA Configuration Mechanisms
Sander, O.; Braun, L.; Huebner, M.; Becker, J.
2008. Reconfigurable computing: architectures, tools and applications. Ed.: R. Woods, 312–317, Springer-Verlag
Zeitschriftenaufsätze
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC
Kuehnle, M.; Huebner, M.; Becker, J.; Deledda, A.; Mucci, C.; Ries, F.; Coppola, A. M.; Pieralisi, L.; Locatelli, R.; Maruccia, G.; DeMarco, T.; Campi, F.
2008. IEEE Design & Test of Computers, 25 (5), 442–451
An Optically Powered Video Camera Link
Boettger, G.; Dreschmann, M.; Klamouris, C.; Huebner, M.; Rger, M.; Kueng, T.; Becker, J.; Freude, W.; Leuthold, J.
2008. IEEE Photonics Technology Letters, 20 (1), 39–41
Current Trends on Reconfigurable Computing
Becker, J.; Huebner, M.; Woods, R.; Long, P.; Esser, R.; Torres, L.
2008. International Journal of Reconfigurable Computing, 2008, 918525/1–1
Proceedingsbeiträge
Towards Novel Approaches in Design Automation for FPGA Power Optimization
Noguera, J.; Esser, R.; Paulsson, K.; Hübner, M.; Becker, J.
2008. Integrated Circuit and System Design : Power and Timing Modeling, Optimization and Simulation : 18th International Workshop, PATMOS 2008, Revised Selected Papers, Lisbon, Portugal, 10th - 12th September 2008. Ed.: L. Svensson, 419–428, Springer-Verlag. doi:10.1007/978-3-540-95948-9_42
Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain
Huebner, M.; Becker, J.; Sander, O.; Traub, M.
2008. Proceedings of the 2008 International Conference on Field-Programmable Technology, December 7 - 10, 2008, the Grand Formosa Regent Hotel, Taipei, Taiwan. Ed.: T. El-Ghazawi, 97–104, Institute of Electrical and Electronics Engineers (IEEE)
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems
Becker, J.; Huebner, M.; Esser, R.; Herkersdorf, A.; Stechele, W.; Lauer, V.
2008. Proceedings of the Design, automation and test in Europe, 2008, DATE ’08, Munich, Germany, 10 - 14 March 2008, xlii, IEEE Service Center
An Interface for a Decentralized 2d-Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing
Schuck, C.; Haetzer, B.; Becker, J.
2008. Workshop Proceedings / 4th International Workshop on Reconfigurable, Communication Centric System-on-Chips (ReCoSoC), July 9-11, 2008, Barcelona, Spain, Barcelona
Dynamic Reconfiguration of Nano Architectures using Application Independent Fault Detection
Niknahad, M.; Schuck, C.; Huebner, M.; Becker, J.
2008. Second AETHER - MORPHEUS Workshop- Autumn School ’From Reconfigurable to Self - Adaptive Computing’ (AMWAS’08), October 7-9, 2008, Lugano, Switzerland, Lugano
Depth First Traversal Algorithm for Efficient Build-in Self-Test in Nano Fabrics
Niknahad, M.; Becker, J.
2008. Workshop Proceedings / 4th International Workshop on Reconfigurable, Communication Centric System-on-Chips (ReCoSoC), July 9-11, 2008, Barcelona, Spain, 4, Barcelona
An Exploitation of Reconfigurable Hardware Architectures for Car-to-Car Communication Considering Automotive
Sander, O.; Glas, B.; Becker, J.; Mueller-Glaser, K. D.
2008. FISITA 2008 - 32nd World Automotive Congress, 14 - 19 September 2008, Munich, Germany; 1 CD-Rom, München
A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA
Klimm, A.; Sander, O.; Becker, J.; Subileau, S.
2008. Architecture of Computing Systems - ARCS 2008 : 21st International Conference, February 25-28, 2008, Dresden, Germany. Ed.: U. Brinkschulte, 188–201, Springer-Verlag
FPGA Based Stepper Motor Control Function Exploiting Run-Time Reconfiguration
Dahm, N.; Huebner, M.; Becker, J.
2008. Workshop Proceedings / 4th International Workshop on Reconfigurable Communication Centric System-on-Chips (ReCoSoC), July 9-11, 2008, Barcelona, Spain, 4, Barcelona
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization
Paulsson, K.; Huebner, M.; Becker, J.
2008. FPL 2008 - International Conference on Field Programmable Logic and Applications, 8 - 10 Sept. 2008, Heidelberg, Germany. Ed.: U. Kebschull, 699–700, Institute of Electrical and Electronics Engineers (IEEE)
Data path driven waveform-like reconfiguration
Braun, L.; Paulsson, K.; Kromer, H.; Huebner, M.; Becker, J.
2008. International Conference on Field Programmable Logic and Applications (FPL 2008), 8-10 Sept. 2008, Heidelberg, Germany, 607–610, IEEE Computer Society
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput
Claus, C.; Zhang, B.; Stechele, W.; Braun, L.; Huebner, M.; Becker, J.
2008. FPL 2008 - International Conference on Field Programmable Logic and Applications, 8 - 10 September 2008, Heidelberg, Germany. Ed.: U. Kebschull, 535–538, Institute of Electrical and Electronics Engineers (IEEE)
New dimensions for multiprocessor architectures: On demand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach
Goehringer, D.; Huebner, M.; Perschke, T.; Becker, J.
2008. FPL 2008 - International Conference on Field Programmable Logic and Applications, 8 - 10 Sept. 2008, Heidelberg, Germany. Ed.: U. Kebschull, 495–498, Institute of Electrical and Electronics Engineers (IEEE)
SPP1148 booth: Coarse-grained reconfiguration
Thomas, A.; Becker, J.; u. a.
2008. FPL 2008 - International Conference on Field Programmable Logic and Applications, 8 - 10 September 2008, Heidelberg, Germany. Ed.: U. Kebschull, 349–349, Institute of Electrical and Electronics Engineers (IEEE)
SPP1148 booth: Fine grain reconfigurable architectures
Braun, L.; Schwalb, T.; Graf, P.; Hübner, M.; Becker, J.; u. a.
2008. International Conference on Field Programmable Logic and Applications (FPL 2008), 8-10 Sept. 2008, Heidelberg, Germany, 348–348, Institute of Electrical and Electronics Engineers (IEEE)
Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures
Morra, C.; Cardoso, J. M. P.; Bispo, J.; Becker, J.
2008. SASP 2008 - IEEE Symposium on Application Specific Processors, 8 - 9 June 2008, Anaheim, CA, 34–41, Institute of Electrical and Electronics Engineers (IEEE)
A Web Server Based Edge Detector Implementation in FPGA
Shukla, S.; Bergmann, N. W.; Becker, J.
2008. ISVLSI 2008 - IEEE Computer Society Annual Symposium on VLSI, 7 - 9 April 2008, Montpellier, France, 441–446, IEEE Computer Society
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs
Paulsson, K.; Viereck, U.; Huebner, M.; Becker, J.
2008. ISVLSI ’08 - IEEE Computer Society Annual Symposium on VLSI, 7 - 9 April 2008, Montpellier, France, 304–309, IEEE Computer Society
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era
Becker, J.
2008. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), 7-9 April 2008, Montpellier, France, 1–2, IEEE Computer Society
A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates
Glas, B.; Klimm, A.; Schwab, D.; Mueller-Glaser, K. D.; Becker, J.
2008. RSP 2008 - The 19th IEEE/IFIP International Symposium on Rapid System Prototyping, 2 - 5 June 2008, Monterey, California, 135–141, Institute of Electrical and Electronics Engineers (IEEE)
A self adaptive interfacing concept for consumer device integration into automotive entities
Glas, B.; Klimm, A.; Sander, O.; Mueller-Glaser, K. D.; Becker, J.
2008. IPDPS 2008 - IEEE International Symposium on Parallel and Distributed Processing, 14 - 18 April 2008, Miami, Florida, USA, 1–6, Institute of Electrical and Electronics Engineers (IEEE)
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores
Klimm, A.; Braun, L.; Becker, J.
2008. IPDPS 2008 - IEEE International Symposium on Parallel and Distributed Processing, 14 - 18 April 2008, Miami, Florida, USA, 1–7, Institute of Electrical and Electronics Engineers (IEEE)
A framework for dynamic 2D placement on FPGAs
Schuck, C.; Kuehnle, M.; Huebner, M.; Becker, J.
2008. IPDPS 2008 - IEEE International Symposium on Parallel & Distributed Processing, 14 - 18 April 2008, Miami, FL, 1–7, IEEE Service Center
Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems
Huebner, M.; Braun, L.; Goehringer, D.; Becker, J.
2008. IPDPS 2008 - IEEE International Symposium on Parallel and Distributed Processing, 14 - 18 April 2008, Miami, Florida, USA, 1–6, Institute of Electrical and Electronics Engineers (IEEE)
Runtime adaptive multi-processor system-on-chip: RAMPSoC
Goehringer, D.; Huebner, M.; Schatz, V.; Becker, J.
2008. IPDPS 2008 - IEEE International Symposium on Parallel and Distributed Processing, 14 - 18 April 2008, Miami, Florida, USA, 1–7, Institute of Electrical and Electronics Engineers (IEEE)
STUD2COMM - RP-design of an embedded system in education based on a process assessment model
Kuehnle, M.; Hillenbrand, M.; Becker, J.; Mueller-Glaser, K. D.
2008. RC education 2008 - The 3rd International Workshop on Reconfigurable Computing Education, April 10, 2008, Montpellier, France, Montpellier
Towards Novel Approaches in Design Automation for FPGA Power Optimization
Becker, J.; Huebner, M.; Paulsson, K.; Esser, R.; Noguera, J.
2008. Integrated circuit and system design - power and timing modeling, optimization and simulation : 18th International Workshop, PATMOS 2008, September 10 - 12, 2008, Lisbon, Portugal; revised selected papers. Ed.: L. Svensson, 419–428, Springer-Verlag
A systems engineering laboratory in the context of the "Bologna Process"
Kuehnle, M.; Hillenbrand, M.; Becker, J.; Mueller-Glaser, K. D.
2008. Poster Session / EWME 2008 - 7th European Workshop on Microelectronics Education, May 28 - 30, 2008, Budapest, Hungary, 30 Folien, Budapest
Dissertationen
Intelligente Steuerungsmechanismen für laufzeitadaptive Hardware-/ Softwaresysteme. Dissertation
Ullmann, M.
2008. Universität Karlsruhe (TH)
2007
Buchaufsätze
Exploitation of Run-TIme Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems
Paulsson, K.; Huebner, M.; Bayar, S.; Becker, J.
2007. Presentation / ReCoSoc2007 - Reconfigurable, Communication Centric System-on-Chips, June 18 - 20, Montpellier, France, Montpellier
Zeitschriftenaufsätze
Dynamic and Partial FPGA Exploitation
Becker, J.; Huebner, M.; Hettich, G.; Constapel, R.; Eisenmann, J.; Luka, J.
2007. Proceedings of the IEEE, 95 (2), 438–452
New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur)
Thomas, A.; Becker, J.
2007. it - Information Technology, 49 (3), 165–173
Proceedingsbeiträge
Exploitation of Run-TIme Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems
Paulsson, K.; Huebner, M.; Bayar, S.; Becker, J.
2007. Proceedings of the International Workshop on Reconfigurable Communication-centric System-on-Chip, June 18th-20th, Montpellier, France
Modulares Systemkonzept fur einen FPGA basierten Automotive Gateway = Modular system concept for FPGA-based Automotive Gateway
Becker, J.; Huebner, M.; Sander, O.; Dreschmann, M.; Luka, J.; Traub, M.; Weber, T.
2007. Proceedings of the 13. Internationaler Kongress Elektronik im Kraftfahrzeug, Tagung Baden-Baden, 10. und 11. Oktober 2007, 223–232, VDI Verlag
New tool support and architectures in adaptive reconfigurable computing
Huebner, M.; Becker, J.; Donlin, A.
2007. Proceedings of the 2007 IFIP International Conference on Very Large Scale Integration, Atlanta, GA, 15 - 17 October 2007, 134–139, IEEE Service Center
A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures
Graf, P.; Huebner, M.; Mueller-Glaser, K. D.; Becker, J.
2007. FPL 2007 - International Conference on Field Programmable Logic and Applications, 27 - 29 Aug. 2007, Amsterdam, The Netherlands, 722–725, IEEE Operations Center
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications
Braun, L.; Huebner, M.; Becker, J.; Perschke, T.; Schatz, V.; Bach, S.
2007. FPL 2007 - International Conference on Field Programmable Logic and Applications, 27-29 Aug. 2007, Amsterdam, The Netherlands. Ed.: K. Bertels, 688–691, IEEE Operations Center
H. 264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture
Ganesan, M. K. A.; Singh, S.; May, F.; Becker, J.
2007. FPL 2007 - International Conference on Field Programmable Logic and Applications, 27 - 29 Aug. 2007, Amsterdam, The Netherlands, 467–471, IEEE Operations Center
On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the AETHER Project
Paulsson, K.; Huebner, M.; Becker, J.; Philippe, J.-M.; Gamrat, C.
2007. FPL 2007 - International Conference on Field Programmable Logic and Applications, 27 - 29 Aug. 2007, Amsterdam, The Netherlands, 415–422, IEEE Operations Center
MORPHEUS: Heterogeneous Reconfigurable Computing
Thoma, F.; Kuehnle, M.; Bonnot, P.; Panainte, E. M.; Bertels, K.; Goller, S.; Schneider, A.; Schuler, E.; Mueller-Glaser, K. D.; Becker, J.
2007. FPL 2007 - International Conference on Field Programmable Logic and Applications, 27 - 29 Aug. 2007, Amsterdam, The Netherlands, 409–414, IEEE Operations Center
artNoC - A Novel Multi-Functional Router Architecture for Organic Computing
Schuck, C.; Lamparth, S.; Becker, J.
2007. FPL 2007 - International Conference on Field Programmable Logic and Applications, 27 - 29 Aug. 2007, Amsterdam, The Netherlands, 371–376, IEEE Operations Center
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs
Paulsson, K.; Huebner, M.; Auer, G.; Dreschmann, M.; Chen, L.; Becker, J.
2007. FPL 2007 - International Conference on Field Programmable Logic and Applications, 27 - 29 Aug. 2007, Amsterdam, The Netherlands, 351–356, IEEE Operations Center
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs
Boden, M.; Fiebig, T.; Meissner, T.; Rulke, S.; Becker, J.
2007. IPDPS 2007 - IEEE International Parallel and Distributed Processing Symposium, 26-30 March 2007, Long Beach, CA, 1–8, Institute of Electrical and Electronics Engineers (IEEE)
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks
Shukla, S.; Bergmann, N. W.; Becker, J.
2007. IPDPS 2007 - IEEE International Parallel and Distributed Processing Symposium, 26-30 March 2007, Long Beach, CA, 1–7, Institute of Electrical and Electronics Engineers (IEEE)
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
Brito, A. V.; Kuehnle, M.; Melcher, E. U. K.; Becker, J.
2007. IPDPS 2007 - IEEE International Parallel and Distributed Processing Symposium, 26-30 March 2007, Long Beach, CA, 1–7, Institute of Electrical and Electronics Engineers (IEEE)
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements
Morra, C.; Cardoso, J. M. P.; Becker, J.
2007. IPDPS 2007 - IEEE International Parallel and Distributed Processing Symposium, 26-30 March 2007, Long Beach, CA, 1–8, Institute of Electrical and Electronics Engineers (IEEE)
Communication Architectures for Dynamically Reconfigurable FPGA Designs
Pionteck, T.; Albrecht, C.; Koch, R.; Maehle, E.; Huebner, M.; Becker, J.
2007. IPDPS 2007 - IEEE International Parallel and Distributed Processing Symposium, 26-30 March 2007, Long Beach, CA, 1–8, Institute of Electrical and Electronics Engineers (IEEE)
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC
Brito, A. V.; Kuehnle, M.; Huebner, M.; Becker, J.; Melcher, E. U. K.
2007. ISVLSI 2007 - IEEE Computer Society Annual Symposium on VLSI, 9-11 March 2007, Porto Alegre, Brazil, 35–40, IEEE Computer Society
Optically Powered Video Camera Link
Boettger, G.; Huebner, M.; Klamouris, C.; Dreschmann, M.; Bett, A. W.; Becker, J.; Freude, W.; Leuthold, J.; Roeger, M.
2007. ECOC 07 - 33rd European Conference and Exhibition on Optical Communication, September 16 - 20, 2007, Berlin, Germany, VDE Verlag
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs
Huebner, M.; Braun, L.; Becker, J.
2007. ISVLSI 2007 - IEEE Computer Society Annual Symposium on VLSI, 09 - 11 May 2007, Porto Alegre, Brazil. Ed.: J. Becker, 41–46, IEEE Computer Society
A System-on-Chip Audio Decoder - a Project oriented SoC Design for Education
Kuehnle, M.; Koenig, R.; Thoma, F.; Becker, J.
2007. First AETHER - MORPHEUS Workshop - Autumn School ’From Reconfigurable to Self - Adaptive Computing’ (AMWAS’07), October 8-11, 2007, Paris, France, Paris
A Mixed-Signal System-on-Chip Audio Decoder Design for Education
Koenig, R.; Thomas, A.; Kuehnle, M.; Becker, J.; Crocoll, E.; Siegel, M.
2007. RC Education - 2nd International Workshop on Reconfigurable Computing Education, May 12, 2007, Porto Allegre, Brasil, Porto Allegre
2006
Zeitschriftenaufsätze
Dynamic and Partial FPGA Self-Reconfiguration Using Real-Time LUT-Based Network-On-Chip Adaptive Topologies for Xilinx FPGAs
Huebner, M.; Becker, J.
2006. Journal Integrated Circuits and Systems, 1 (4), 43–53
Physical 2D Morphware and Power Reduction Methods for Everyone
Becker, J.; Huebner, M.; Paulsson, K.
2006. Dagstuhl Seminar Proceedings, 06141, 10/1–5
Proceedingsbeiträge
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
Morra, C.; Sackmann, M.; Shukla, S.; Becker, J.; Hartenstein, R.
2006. FPL 2006 - International Conference on Field Programmable Logic and Applications, 28 - 30 Aug. 2006, Madrid, Spain, 1–4, IEEE Operations Center
Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System
Becker, J. E.; Bieser, C.; Becker, J.; Müller-Glaser, K. D.
2006. 2006 IEEE International Symposium on Industrial Electronics, 9-13 July 2006, Montreal, Quebec, Canada; Vol. 4, 3184–3189, Institute of Electrical and Electronics Engineers (IEEE)
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs
Huebner, M.; Schuck, C.; Becker, J.
2006. IPDPS 2006 - 20th International Parallel and Distributed Processing Symposium, 2006, 25 - 29 April 2006, Rhodes Island, Greece, 8 S., IEEE Service Center
Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems
Ullmann, M.; Becker, J.
2006. IPDPS 2006 - 20th International Parallel and Distributed Processing Symposium, 25 - 29 April 2006, Rhodes Island, Greece, 8 S., IEEE Service Center
A high-level target-precise model for designing reconfigurable HW tasks
Boden, M.; Rulke, S.; Becker, J.
2006. IPDPS 2006 - 20th International Parallel and Distributed Processing Symposium, 2006, 25 - 29 April 2006, Rhodes Island, Greece, 8 S., IEEE Service Center
Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration
Paulsson, K.; Huebner, M.; Becker, J.
2006. First NASA/ESA Conference on Adaptive Hardware and Systems, 15 - 18 June 2006, Istanbul, Turkey. Ed.: A. Stoic, 288–291, IEEE Computer Society
Dynamic hardware multiplexing: improving adaptability with a run time reconfiguration manager
Becker, J.; Benoit, P.; Torres, L.; Sassatelli, G.; Robert, M.; Cambon, G.
2006. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2006, 2 - 3 March 2006, Karlsruhe, Germany. Ed.: J. Becker, 6 S., IEEE Computer Society
Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs
Paulsson, K.; Huebner, M.; Jung, M.; Becker, J.
2006. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2 - 3 March 2006, Karlsruhe, Germany. Ed.: J. Becker, 6 S., IEEE Computer Society
QUKU: a two-level reconfigurable architecture
Shukla, S.; Bergmann, N. W.; Becker, J.
2006. IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2 - 3 March 2006, Karlsruhe, Germany. Ed.: J. Becker, 6 S., IEEE Computer Society
New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits
Huebner, M.; Schuck, C.; Kuehnle, M.; Becker, J.
2006. Proceedings / IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, 2 - 3 March 2006, Karlsruhe, Germany, 6 S., IEEE Computer Society
Realization of Real-Time Control Flow Oriented Automotive Applications on a Soft-core Multiprocessor System based on Xilinx Virtex II FPGAs
Paulsson, K.; Hübner, M.; Zou, H.; Becker, J.
2006. Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC ’05), February 22 - 23, 2005, Algarve, Portugal, 103–110, Taylor and Francis
Using Rewriting Logic to Generate Differrent Implementations of Polynomial Approximations in Coarse-Grained Architectures
Morra, C.; Sackmann, M.; Becker, J.; Hartenstein, R.
2006. Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip ( ReCoSoC), July 2006, Montpellier, France. Ed.: G. Sassatelli, 46–51, Univ. Montpellier II
Optically Powered Video Camera Network
Boettger, G.; Huebner, M.; Dreschmann, M.; Klamouris, C.; Paulsson, K.; Kueng, T.; Bett, A. W.; Becker, J.; Freude, W.; Leuthold, J.
2006. Kommunikationskabelnetze - Vorträge der 13. ITG-Fachtagung, 12. bis 13. Dezember 2006, Köln, Germany, 123–124, VDE Verlag
Tutorial on Macro Design for Dynamic and Partially Reconfigurable Systems
Huebner, M.; Becker, J.
2006. RC-Education 2006 - 1st International Workshop on Reconfigurable Computing Education March 1, 2006, Karlsruhe, Germany, Universität Karlsruhe (TH)
Seamless Design Flow for Run-Time Reconfigurable Automotive Systems
Huebner, M.; Becker, J.
2006. DATE 2006 - Design, Automation & Test in Europe Conference & Exhibition, 6-10 March 2006, Munich, Germany, Institute of Electrical and Electronics Engineers (IEEE)
On-Line Optimization of FPGA Power-Dissipation by Exploiting Run-time Adaption of Communication Primitives
Paulsson, K.; Huebner, M.; Becker, J.
2006. Chip on the mountains: SBCCI 2006 - Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, August 28 - September 1, 2006, Ouro Preto, MG, Brazil, Association for Computing Machinery (ACM)
Novel HW/SW Design Methodologies for Ad-Hoc Sensor Networks in Future Applications
Chandra-Sekaran, A.; Sander, O.; Paulsson, K.; Huebner, M.; Becker, J.; Mueller-Glaser, K. D.
2006. Proceedings of the 8th International Workshop on Computer Science and Information Technologies (CSIT), 28-29 September, 2006, Karlsruhe, Germany, Universität Karlsruhe (TH)
Run-time Reconfigurabilility and other Future Trends
Becker, J.; Huebner, M.
2006. Chip on the mountains: SBCCI 2006 - Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, August 28 - September 1, 2006, Ouro Preto, MG, Brazil, 9–11, Association for Computing Machinery (ACM)
Exploiting Dynamic and Partial Reconfiguration for FPGAs - Toolflow, Architecture and System Integration
Huebner, M.; Becker, J.
2006. Chip on the mountains: SBCCI 2006 - Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, August 28 - September 1, 2006, Ouro Preto, MG, Brazil, 1–4, Association for Computing Machinery (ACM)
Optically powered platform with Mb/s transmission over a single fiber
Klamouris, C.; Boettger, G.; Huebner, M.; Dreschmann, M.; Paulsson, K.; Kueng, T.; Becker, J.; Freude, W.; Leuthold, J.
2006. ECOC 2006 - 32nd European Conference on Optical Communication, 24-28 September, Cannes, France; 1 CD-Rom, 461–462, SEE
Dynamically Reconfigurable Hardware: "A promising Way to On-Line Diagnosis, Fault-Tolerance and Reliability
Becker, J.; Huebner, M.
2006. ECSIS Symposium on Intelligent Systems for Defense and Security (ISDS) part of the 4th European Conference on Intelligent Systems and Technologies (ECIT), September 20-21, 2006, Iasi, Romani, Iasi
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems
Becker, J.; Huebner, M.; Ullmann, M.
2006. VLSI-SOC: From Systems to Chips - Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1 - 3, 2003, Darmstadt, Germany. Ed.: M. Glesner, 119–132, Springer US
Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath
Becker, J.; Thomas, A.; Scheer, M.
2006. VLSI-SOC: From Systems to Chips - Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1 - 3, 2003, Darmstadt, Germany. Ed.: M. Glesner, 263–279, Springer US
2005
Buchaufsätze
Automotive Control Unit Optimisation Perspectives: Body Functions on-Demand by Dynamic Reconfiguration
Becker, J.; Hübner, M.; Müller-Glaser, K. D.; Constapel, R.; Luka, J.; Eisenmann, J.
2005. DATE 2005 - Design, Automation and Test in Europe, 7 - 11 March 2005, Munich, Germany, IEEE Computer Society
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems
Ullmann, M.; Jin, W.; Becker, J.
2005. DATE 2005 - Design, Automation and Test in Europe, 7 - 11 March 2005, Munich, Germany; Vol. 3. Ed.: N. Wehn, 259–264, IEEE Computer Society
Zeitschriftenaufsätze
Scalable processor instruction set extension
Becker, J.; Thomas, A.
2005. IEEE Design & Test of Computers, 22 (2), 136–148
Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen
Ullmann, M.; Becker, J.; Braendle, K.
2005. it - Information Technology, 47 (4), 201–206
Real-time configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation
Huebner, M.; Ullmann, M.; Becker, J.
2005. International Journal of Embedded Systems, 1 (3/4), 263–273
Proceedingsbeiträge
Realization of Real-Time Control Flow Oriented Automotive Applications on a Soft-core Multiprocessor System based on Xilinx Virtex II FPGAs
Paulsson, K.; Huebner, M.; Zou, H.; Becker, J.
2005. Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC ’05), Algarve, Portugal, February, 2005, 103–110
Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs
Huebner, M.; Paulsson, K.; Stitz, M.; Becker, J.
2005. 18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005, 39–44, Springer-Verlag
Models and Tools for the Dynamic Reconfiguration of FPGAs
Donlin, A.; Huebner, M.; Becker, J.
2005. IEEE International SOC Conference : proceedings, September 25-28, 2005, Hilton Washington Dulles Airport, Herndon, VA. Ed.: Dong Ha ..., 315–316, Institute of Electrical and Electronics Engineers (IEEE)
Hardware Enhanced Function Allocation Management in Reconfigurable Systems
Ullmann, M.; Jin, W.; Becker, J.
2005. Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium, 156–163, Institute of Electrical and Electronics Engineers (IEEE). doi:10.1109/IPDPS.2005.240
From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling
Bieser, C.; Mueller-Glaser, K. D.; Becker, J.
2005. 2005 IEEE International Conference on Microelectronic Systems Education (MSE ’05) : June 12 - 13, 2005, Anaheim, California, USA, 51–52, Institute of Electrical and Electronics Engineers (IEEE)
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics
Huebner, M.; Becker, J.; Paulsson, K.; Thomas, A.
2005. Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005, Univ. Montpellier II
Automotive Control Unit Optimisation Perspectives: Body Functions on-Demand by Dynamic Reconfiguration
Becker, J.; Huebner, M.; Müller-Glaser, K. D.; Constapel, R.; Luka, J.; Eisenmann, J.
2005. DATE 2005 - Design, Automation and Test in Europe, 7 - 11 March 2005, Munich, Germany ; Vol. 1, Institute of Electrical and Electronics Engineers (IEEE)
Energy Model of Networks-on-Chip and a Bus
Wolkotte, P. T.; Smit, G. J. M.; Kavaldjiev, N.; Becker, J. E.; Becker, J.
2005. Proceedings / 2005 International Symposium on System-on-Chip, 15 - 17 Nov. 2005, Tampere, Finland. Ed.: J. Nurmi, 82–85, IEEE Operations Center
Overview of the 4S Project
Smit, G. J. M.; Schuler, E.; Becker, J.; Quevremont, J.; Brugger, W.
2005. Proceedings / 2005 International Symposium on System-on-Chip, 15 - 17 Nov. 2005, Tampere, Finland, 70–73, IEEE Operations Center
Energy efficient NoC for best effort communication
Wolkotte, P. T.; Smit, G. J. M.; Becker, J. E.
2005. FPL 2005 - International Conference on Field Programmable Logic and Applications, 24 - 26 Aug. 2005, Tampere, Finland. Ed.: T. Rissa, 197–202, IEEE Operations Center. doi:10.1109/FPL.2005.1515722
Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores
Huebner, M.; Paulsson, K.; Becker, J.
2005. Proceedings / 19th IEEE International Parallel and Distributed Processing Symposium, April 4 - 8, 2005, Denver, Colorado, 149a - 149a, IEEE Computer Society
Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures Based on Xilinx Virtex-II FPGAs
Hübner, M.; Paulsson, K.; Stitz, M.; Becker, J.
2005. ARCS 2005 - 18th International Conference on Architecture of Computing Systems ’System Aspects in Organic and Pervasive Computing’, March 14 - 17, 2005, Innsbruck, Austria, Innsbruck
Models and Tools for the Dynamic Reconfiguration of FPGAs
Donlin, A.; Huebner, M.; Becker, J.
2005. Proceedings / IEEE International SOC Conference, September 25 - 28, 2005, Hilton Washington Dulles Airport, Herndon, VA. Ed.: D. Ha, 313–316, IEEE Operations Center
Hardware Enhanced Function Allocation Management in Reconfigurable Systems
Ullmann, M.; Jin, W.; Becker, J.
2005. Presentation at the RAW 2005 - 12th Reconfigurable Architectures Workshop, April 4 - 5, 2005, Denver, Colorado, USA, Denver
Hardware/software co-training lab: from VHDL bit-level coding up to CASE-Tool based system modeling
Bieser, C.; Müller-Glaser, K. D.; Becker, J.
2005. Proceedings / 2005 IEEE International Conference on Microelectronic Systems Education (MSE ’05), 12 - 13 June 2005, Anaheim, California, USA, 51–52, IEEE Computer Society. doi:10.1109/MSE.2005.34
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations
Morra, C.; Becker, J.; Ayala-Rincon, M.; Hartenstein, R.
2005. FPL 2005 - International Conference on Field Programmable Logic and Applications, 24 - 26 Aug. 2005, Tampere, Finland. Ed.: T. Rissa, 25–30, IEEE Operations Center
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics
Hübner, M.; Becker, J.; Paulsson, K.; Thomas, A.
2005. Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), June 2005, Montpellier, France. Ed.: G. Sassatelli, 35–42, Univ. Montpellier II
Multi-grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures
Thomas, A.; Becker, J.
2005. ISVLSI 2005 - IEEE Computer Society Annual Symposium on VLSI, May 11-12, 2005, Tampa, Florida, 118–123, IEEE Computer Society
Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment
Thomas, A.; Becker, J.
2005. Proceedings / IEEE International SOC Conference, September 25 - 28, 2005, Herndon, VA. Ed.: D. Ha, 239–242, IEEE Operations Center
Multi-grained Reconfigurable Harware Architecture with Online-Adaptive Routing Techniques
Thomas, A.; Becker, J.
2005. IFIP VLSI-SOC 2005 - IFIP International Conference on Very Large Scale Integration, October 17-19, 2005, Perth, Australia, Perth
Design Of Optimized Reconfigurable HW Tasks Using Operation Graph Signatures
Boden, M.; Ruelke, S.; Becker, J.
2005. Proceedings / 8th Euromicro Conference on Digital System Design, 30 Aug. - 3 Sept. 2005, Porto, Portugal. Ed.: Ch. Wolinski, IEEE Computer Society
2004
Proceedingsbeiträge
CARUSO - Project Goals and Principal Approach
Brinkschulte, U.; Becker, J.; Dorfmueller-Ulhaas, H.; Koenig, R.; Uhrig, S.; Ungerer, T.
2004. GI-Workshop on Organic Computing, Ulm, Germany, 2004, 616–620
Formale Verifikation eines Sonet/SDH Framers
Becker, J.; Thomas, A.; Heinkel, U.; Winkelmann, K.; Bormann, J.
2004. Vortrag / Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 7. GIT/ITG/GMM-Workshop Modellierung und Verifikation. Hrsg.: D. Stoffel, 280, Shaker Verlag
CARUSO - Project Goals and Principal Approach
Brinkschulte, U.; Becker, J.; Dorfmüller-Ulhaas, H.; Koenig, R.; Uhrig, S.; Ungerer, T.
2004. Informatik 2004, Informatik verbindet - Beiträge der 34. Jahrestagung der Gesellschaft für Informatik e.V. (GI), 20. - 24. September 2004, Ulm, Vol. 2. Hrsg.: P. Dadam, 616–620, Gesellschaft für Informatik (GI)
Real-time LUT-based Network Topologies for dynamic and partial FPGA Self-Reconfiguration
Huebner, M.; Becker, T.; Becker, J.
2004. Chip on the reefs : SBCCI 2004 - Proceedings of the 17th Symposium on Integrated Circuits and Systems Design, September 7 - 11, 2004, Porto de Galinhas, Pernambuco, Brazil, 28–32, Association for Computing Machinery (ACM)
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities
Ullmann, M.; Huebner, M.; Grimm, B.; Becker, J.
2004. Proceedings / Field programmable logic and application - 14th international conference (FPL 2004), August 30 - September 1, 2004, Antwerp, Belgium. Ed.: J. Becker, 454–463, Springer-Verlag
Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration
Huebner, M.; Ullmann, M.; Weissel, F.; Becker, J.
2004. Presentation at the RAW 2004 - 11th Reconfigurable Architectures Workshop, April 26. - 27. 2004, Santa Fé, USA, Santa Fé
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration
Ullmann, M.; Grimm, B.; Huebner, M.; Becker, J.
2004. Presentation at the RAW 2004 - 11th Reconfigurable Architectures Workshop, April 26 - 27 2004, Santa Fé, USA, Santa Fé
Dynamic Adaptive Routing Techniques In Multigrain Dynamic Reconfigurable Hardware Architectures
Thomas, A.; Becker, J.
2004. FPL 2004 - Field-programmable logic and applications, 14th International Conference, August 30 - September 1, 2004, Antwerp, Belgium, 115–124, Springer-Verlag
Aufbau- und Strukturkonzepte einer adaptiven multigranularen rekonfigurierbaren Hardwarearchitektur
Thomas, A.; Becker, J.
2004. ARCS 2004 - Organic and pervasive computing, March 26, 2004, Augsburg; Workshop Proceedings. Hrsg.: U. Brinkschulte, 165–174, Ges. für Informatik
Formale Verifikation eines Sonet/SDH Framers
Thomas, A.; Becker, J.; Heinkel, U.; Winkelmann, K.; Bormann, J.
2004. DASS 2004 - Dresdner Arbeitstagung Schaltungs- und Systementwurf "Intellectual Property Prinzipien-Workshop", 19.- 20. April 2004, Dresden, Fraunhofer Institut
Adaptive DMA-based I/O Interfaces for Data Stream Handling in Multi-grained Reconfigurable Hardware Architectures
Thomas, A.; Zander, T.; Becker, J.
2004. Chip on the reefs : SBCCI 2004 - Proceedings of the 17th Symposium on Integrated Circuits and Systems Design, September 7 - 11, 2004, Porto de Galinhas, Pernambuco, Brazil, 141–146, Association for Computing Machinery (ACM). doi:10.1145/1016568.1016609
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems
Huebner, M.; Ullmann, M.; Braun, L.; Klausmann, A.; Becker, J.
2004. FPL 2004 - Field-programmable logic and applications, 14th international conference, August 30 - September 1, 2004, Antwerp, Belgium, 1037–1041, Springer-Verlag
Anwendungsspezifische IP-Generierung für zukünftige SoC-Implementierungen in mobilen Kommunikationssystemen
Thomas, A.; Becker, J. E.; Becker, J.
2004. DASS 2004 - Dresdner Arbeitstagung Schaltungs- und Systementwurf "Intellectual Property Prinzipien-Workshop", 19.- 20. April 2004, Dresden, Fraunhofer Institut
Proceedingsbände
ARCS 2004 - Organic and pervasive computing : workshop proceedings; March 26, 2004, Augsburg
Brinkschulte, U.; Becker, J.; Fey, D.; Grosspietsch, K.; Hochberger, C.; Maehle, E.; Runkler, T. (Hrsg.)
2004. Ges. für Informatik
Field programmable logic and application - 14th international conference (FPL 2004), August 30 - September 1, 2004, Antwerp, Belgium; Proceedings
Becker, J. (Hrsg.)
2004. Springer-Verlag
ARCS 2004 - Organic and pervasive computing, March 26, 2004, Augsburg; Workshop Proceedings
Becker, J.
2004. (U. Brinkschulte, Hrsg.), Ges. für Informatik
2003
Zeitschriftenaufsätze
Configware and Morphware going Mainstream
Becker, J.; Hartenstein, R. W.
2003. Journal of systems architecture, 49 (4-6). doi:10.1016/S1383-7621(03)00073-0
Configurability for Systems on Silicon: Requirement and Perspective for future VLSI Solutions
Becker, J.
2003. Informacije MIDEM, 33 (4), 236–244
Proceedingsbeiträge
Configurable Systems-on-Chip: Necessity and Perspective for future Microelectronic Solutions
Becker, J.
2003. Proceedings / 15th Symposium on Integrated Circuits and Systems Design : 9 - 14 September 2002, Porto Alegre, Brazil ; [held jointly with SBMicro 2002, International Conference on Microelectronics and Packaging], 379–384, Institute of Electrical and Electronics Engineers (IEEE)
Real-Time Dynamically Run: Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations
Becker, J.; Huebner, M.; Ullmann, M.
2003. VLSI-SoC 2003 ; IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003, 129–134, Techn. Univ
An industrial/academic configurable system-on-chip project (CSoC): coarse-grain XPP-/Leon-based architecture integration
Becker, J.; Thomas, A.; Vorbach, M.; Baumgarte, V.
2003. Proceedings / Design, Automation and Test in Europe Conference and Exhibition (DATE 03), March 3 - 7, 2003, Munich, Germany. Ed.: N. Wehn, 1120–1121, IEEE Computer Society
Power estimation and power measurement of Xilinx Virtex FPGAs: trade-offs and limitations
Becker, J.; Huebner, M.; Ullmann, M.
2003. Proceedings / 16th Symposium on Integrated Circuits and Systems Design (SBCCI 2003),September 8 - 11, 2003, Sao Paulo, Brazil, 283–288, IEEE Computer Society
Efficient processor instruction set extension by asynchronous reconfigurable datapath integration
Becker, J.; Thomas, A.; Scheer, M.
2003. Proceedings / 16th Symposium on Integrated Circuits and Systems Design (SBCCI 2003),September 8 - 11, 2003, Sao Paulo, Brazil, 237–242, IEEE Computer Society
Hardware/software co-training by FPGA/ASIC synthesis and programming of a RISC microprocessor-core
Becker, J. E.; Bieser, C.; Thomas, A.; Müller-Glaser, K. D.; Becker, J.
2003. Proceedings / 2003 IEEE International Conference on Microelectronic Systems Education, June 1 - 2, 2003, Anaheim, California, USA, 134–135, IEEE Computer Society. doi:10.1109/MSE.2003.1205288
Architecture, memory and interface technology integration of an industrial/ academic configurable system-on-chip (CSoC)
Becker, J.; Vorbach, M.
2003. Proceedings / IEEE Computer Society Annual Symposium on VLSI, 2003, 20 - 21 February 2003, Tampa, Florida. Ed.: A. Smailagic, 107–112, IEEE Computer Society
Vorträge
Reconfigurable Computing Systems
Becker, J.
2003. Proceedings Escola de Microeletronica da SBC - Sul (EMICRO 2003), Rio Grande, Brasilien, 2003
2002
Buchaufsätze
Implementing real-time scheduling within a multithreaded Java microcontroller
Uhrig, S.; Liemke, C.; Pfeffer, M.; Becker, J.; Brinkschulte, U.; Ungerer, T.
2002. In: 6th Workshop on Multithreaded Execution, Architecture, and Compilation, MTEAC-6, Istanbul, Turkey 2002. Los Alamitos, Calif. : IEEE Computer Society 2002
Rapid prototyping of FPGA based floating point DSP systems
Ho, C. H.; Leong, M. P.; Leong, P. H. W.; Becker, J.; Glesner, M.
2002. In: 13th IEEE International Workshop on Rapid System Prototyping, RSP 2002, Darmstadt 2002. Los Alamitos, Calif. 2002. S. 19-24
Configurable systems-on-chip: commercial and academic approaches
Becker, J.
2002. In: 9th IEEE International Conference on Electronic Circuits and Systems, ICECS 2002, Dubrovnik, Croatia 2002. [CD-ROM]
Configurable systems-on-chip (CSoC)
Becker, J.
2002. In: 15th Symposium on Integrated Circuits and System Design, SBCCI2002, Porto Alegre, Brazil 2002. Los Alamitos, Calif. : IEEE Computer Society 2002. S. 379-384
Configurable systems-on-chip: challenges and perspectives for industry and universities
Becker, J.
2002. In: International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA’02, Las Vegas 2002. Ed.: T. Plaks. Las Vegas, USA : CSREA Press 2002. S. 109-115
Dynamically reconfigurable systems-on-chip: a core-based industrial/academic SoC synthesis project
Becker, J.; Thomas, A.; Vorbach, M.; Ehlers, G.
2002. In: IEEE Workshop Heterogeneous Reconfigurable SoC, Hamburg 2002
Proceedingsbeiträge
Configurable systems-on-chip (CSoC)
Becker, J.
2002. Proceedings / 15th Symposium on Integrated Circuits and Systems Design, 9 - 14 September 2002, Porto Alegre, Brazil. Ed.: R. Reis, 379–384, IEEE Computer Society
Dynamically Reconfigurable Systems-on-Chip: A Core-based Industrial/Academic SoC Synthesis Project
Becker, J.; Thomas, A.; Vorbach, M.; Ehlers, G.
2002. Proceedings of the IEEE Workshop Heterogeneous Reconfigurable Systems on Chip (SoC), April 2002, Hamburg, Germany
Rapid Prototyping of FPGA based Floating Point DSP Systems
Ho, C.; Leong, M.; Leong, P.; Becker, J.; Glesner, M.
2002. Proceedings / 13th International Workshop on Rapid System Prototyping, 1 - 3 July 2002, Darmstadt, Germany, 19–24, IEEE Computer Society
Implementing Real-time Scheduling within a Multithreaded Java Microcontroller
Uhrig, S.; Liemke, C.; Pfeffer, M.; Becker, J.; Brinkschulte, U.; Ungerer, T.
2002. Proceedings / 6th Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC-6), November 19, 2002, Istanbul, Turkey
Proceedingsbände
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’02)
Arabnia, H. R.; Becker, J.; Gokhale, M.; Gorgon, M.; Platzner, M.
2002. (T. Plaks & P. Athanas, Hrsg.), Las Vegas, USA : CSREA Press 2002
2001
Proceedingsbeiträge
Effiziente IP-basierte Abbildungsverfahren für dynamisch rekonfigurierbare Array-Architekturen
Becker, J.; Pionteck, T.; Glesner, M.
2001. Entwurf integrierter Schaltungen : Präsentationen der ITG-Fachtagung vom 3. bis 5. April 2001 in Dresden / 10. EIS-Workshop, 315–320, VDE Verlag
Adaptive Systems-on-Chip: Architectures, Technologies and Applications
Becker, J.; Pionteck, T.; Glesner, M.
2001. Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design (SBCCI 2001), September 10-15, 2001, Pirenopolis, Brazil, IEEE Computer Society
Architectures, Technologies & CAD for Embedded Systems-on-Chip (SoC)
Becker, J.; Glesner, M.
2001. Conference Proceedings of Electronic Circuits & Systems (ECS 01), September 2001, Bratislava, Slovakia, 97–100, Bratislava
Efficient Mapping of pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures
Becker, J.; Pionteck, T.; Liebau, N.; Glesner, M.
2001. Proceedings / Field-programmable logic and applications - 11th International Conference (FPL 2001), August 27 - 29, 2001, Belfast, Northern Ireland, UK. Ed.: G. Brebner, 584–589, Springer-Verlag
Technologies, Architectures, CAD and Applications of Complex Systems-on-Chip (SoC)
Glesner, M.; Becker, J.; Pionteck, T.
2001. ECCTD ’01 - European Conference on Circuit Theory and Design "Circuit Paradigm in the 21st Century", August 28 - 31, 2001, Espoo, Finland
Simulation, Prototyping and Reconfigurable Hardware Realization of CDMA RAKE-Receiver Algorithms for Flexible Mobile Transceivers
Becker, J.; Pionteck, T.; Glesner, M.
2001. Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2001), June 25 - 28, 2001, Las Vegas, Nevada, USA. Ed.: T. P. Plaks, CSREA Press
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems
Mukherjee, N.; Motgi, J.; Becker, J.; Friebe, A.; Habermann, C.; Glesner, M.
2001. Proceedings / 12th International Workshop on Rapid System Prototyping, RSP 2001, June 25 - 27, 2001, Monterey, Calif., 58 - 63, IEEE Computer Society
Design and Implementation of a Coarse-Grained Dynamically Reconfigurable Hardware Architecture
Becker, J.; Pionteck, T.; Habermann, C.; Glesner, M.
2001. Proceedings / IEEE Computer Society Annual Workshop on VLSI (WVLSI 2001), 19-20 April, 2001, Orlando, Florida
Effiziente IP-basierte Abbildungsverfahren für dynamisch rekonfigurierbare Array-Architekturen
Becker, J.; Pionteck, T.; Glesner, M.
2001. Entwurf integrierter Schaltungen - 10. E.I.S.-Workshop ; Präsentationen der ITG-Fachtagung, 3. bis 5. April 2001, Dresden, 315–320, VDE Verlag