Parallel result validation of AI accelerators using most neuron activation monitor

Background

Automotive system architectures are undergoing radical change. The recent development explosion in sensor technology to support active safety, trends such as IoT, driver assistance systems, electric mobility or autonomous driving make it essential to move away from traditional architectures consisting of networked ECUs or PLCs in favor of more centralized and powerful components.

Task

Inside these components, AI accelerators are ever more common. Validating these accelerators and making them resilient against adversarial attacks is a key requirement for ASIL certification. In this thesis, the possibilities of parallel evaluation using predefined neurons should be evaluated. Modifying an ai accelerator to do this is your task.

Requirements

• Very good knowledge of VHDL, Verilog (through HSC, DHL, or similar lectures) or alternatively in HLS languages such as SystemC, SystemVerilog or Chisel
• Knowledge in deep neural network architectures
• Knowledge in ai hardware accelerator architectures
• Motivation to tackle difficult problems in the space of ai hardware accelerators